AD7143 Analog Devices, AD7143 Datasheet

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... VDRIVE pin for I C serial interface operating voltages between 1.65 V and 3.6 V. The AD7143 is available in a 16-lead × LFCSP-VQ and operates from a 2 3.6 V supply. The operating current consumption is less than 1 mA, falling to 50 μA in low power mode (conversion interval of 400 ms). ...

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... AD7143 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... Timing Specifications............................................................ 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 11 Capacitance Sensing Theory..................................................... 11 Operating Modes........................................................................ 12 Capacitance Sensor Input Configuration.................................... 13 CIN Input Multiplexer Setup ...

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... V 150 mV 0 +0.1 ±1 μA 2.6 3.3 3.6 V 1.65 3 full power mode 20 μA Low power mode, converter idle μA Low power mode, converter idle 4.5 μA Full shutdown, T 2.25 15 μA Full shutdown Rev Page GND IN = −1 mA SINK = 25° 25°C A AD7143 ...

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... AD7143 Table 2. Typical Average Current in Low Power Mode, V Low Power Mode Delay Decimation Rate 200 ms 128 256 400 ms 128 256 600 ms 128 256 800 ms 128 256 Table 3. Maximum Average Current in Low Power Mode, V Low Power Mode Delay Decimation Rate 200 ms 128 ...

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... Start condition setup time, t SU; STA Bus free time between stop and start conditions, t Clock/data rise time Clock/data fall time 200µ OUTPUT PIN C L 50pF 200µ Figure 2. Load Circuit for Digital Output Timing Specifications Rev Page BUF 1.6V AD7143 ...

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... AD7143 ABSOLUTE MAXIMUM RATINGS Parameter VCC to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except 1 Supplies ESD Rating (Human Body Model) Operating Temperature Range Storage Temperature Range Junction Temperature LFCSP_VQ Power Dissipation θ ...

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... General-Purpose Open-Drain Interrupt Output. Programmable polarity; requires pull-up resistor. 15 CIN0 Capacitance Sensor Input. 16 CIN1 Capacitance Sensor Input. PIN 1 INDICATOR 12 SDA CIN2 1 CIN3 2 11 VDRIVE AD7143 CIN4 3 TOP VIEW 10 GND (Not to Scale) CIN5 4 9 VCC Figure 3. Pin Configuration Rev Page AD7143 ...

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... AD7143 TYPICAL PERFORMANCE CHARACTERISTICS 1000 980 DEVICE 1 960 DEVICE 3 940 920 DEVICE 2 900 880 860 840 820 2.7 2.8 2.9 3.0 3.1 3.2 V (V) CC Figure 4. Supply Current vs. Supply Voltage 180 LP_CONV_DELAY = 200ms 160 140 120 LP_CONV_DELAY = 400ms 100 80 LP_CONV_DELAY = 600ms 60 LP_CONV_DELAY = 800ms 40 2.7 2.8 2.9 3.0 3.1 3.2 V (V) CC Figure 5. Low Power Supply Current vs. Supply Voltage, ...

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... Figure 15. Power Supply Square Wave Rejection Rev Page AD7143 CDC OUTPUT CODE 10k 20k 30k 40k 50k 60k CDC OUTPUT CODE Figure 13. 3.3 V Linearity Error 100mV 300mV 200mV 400mV 500mV 1k ...

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... AD7143 32900 32800 32700 32600 32500 32400 32300 PARASITIC 32200 CAPACITANCE 32100 32000 31900 PCB PARASITIC CAPACITANCE (pF) Figure 16. CDC Output Codes vs. Parasitic Capacitance Rev Page ...

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... The AD7143 has an interrupt output, INT , to indicate when new data has been placed into the registers. INT is used to interrupt the host on sensor activation. The AD7143 operates from a 2 3.6 V supply, and is available in a 16-lead × LFCSP_VQ. CAPACITANCE SENSING THEORY The AD7143 uses a method of sensing capacitance known as the shunt method ...

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... EVERY LP_CONV_DELAY ms UPDATE COMPENSATION LOGIC DATA PATH The time taken for the AD7143 to go from a full power state to a reduced power state, once the user stops touching the external sensors, is configurable. Once the sensors are not touched, the PWR_DWN_TIMEOUT bits, in the Ambient Compensation Ctrl 0 Register at Address 0x002, control the amount of time necessary for the device to return to a reduced power state ...

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... CAPACITANCE SENSOR INPUT CONFIGURATION Each input connection from the external capacitance sensors to the AD7143 converter can be uniquely configured by using the registers in Table 38 and Table 39. These registers are used to configure input pin connection setups, sensor offsets, sensor sensitivities, and sensor limits for each stage. Each sensor can be individually optimized ...

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... CAPACITANCE SENSOR OFFSET CONTROL There are two programmable DACs on board the AD7143 to null any capacitance sensor offsets. These offsets are associated with printed circuit board capacitance or capacitance due to any other source, such as connectors ...

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... CIN6 CIN7 Figure 23. CDC Conversion Stages The number of required conversion stages depends completely on the number of sensors attached to the AD7143. Figure 24 shows how many conversion stages are required for each sensor, and how many inputs each sensor requires to the AD7143. AD7143 SEQUENCER ...

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... This feature provides some flexibility for optimizing the conversion time to meet system requirements vs. AD7143 power consumption. For example, maximum power savings is achieved when the LP_CONV_DELAY register is set to 3. With a setting of 3, the AD7143 automatically wakes up, performing a conversion every 800 ms. Table 9. LP_CONV_DELAY Settings LP_CONV_DELAY Bits ...

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... AD7143 automatically forces an internal recalibration. This ensures that the ambient values are recalibrated, regardless of how long the user hovers over a sensor. The AD7143 recalibrates automatically when the measured CDC value exceeds the stored ambient value by an amount determined by PROXIMITY_RECAL_LVL, for a set period know as the recalibration timeout ...

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... AD7143 USER APPROACHES SENSOR HERE CDC CONVERSION SEQUENCE (INTERNAL) PROXIMITY DETECTION (INTERNAL) CALIBRATION (INTERNAL) Figure 27. Full Power Mode Proximity Detection Example with FP_PROXIMITY_CNT = 1 USER APPROACHES SENSOR HERE ...

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... FF_SKIP_CNT = 0000 = no samples skipped SLOW FIFO As shown in Figure 31, a number of FIFOs are implemented on the AD7143. These FIFOs are located in Bank 3 of the on-chip memory. The slow FIFOs are used by the on-chip logic to monitor the ambient capacitance level from each sensor. AVG_FP_SKIP and AVG_LP_SKIP In Register 0x001, Bits[13:12] are the slow FIFO skip control for full power mode, AVG_FP_SKIP ...

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... AD7143 Table 11. FF_SKIP_CNT Settings FF_SKIP_CNT Decimation = 128 0 1.525 × (SEQUENCE_STAGE_NUM + 3.072 × (SEQUENCE_STAGE_NUM + 4.608 × (SEQUENCE_STAGE_NUM + 6.144 × (SEQUENCE_STAGE_NUM + 7.68 × (SEQUENCE_STAGE_NUM + 9.216 × (SEQUENCE_STAGE_NUM + 10.752 × (SEQUENCE_STAGE_NUM + 12.288 × (SEQUENCE_STAGE_NUM + 13.824 × (SEQUENCE_STAGE_NUM + 15.25 × ...

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... COMPARATOR 3: USED TO ENABLE THE SLOW FILTER UPDATE RATE. THE SLOW FILTER IS UPDATED WHEN SLOW FILTER EN IS SET AND PROXIMITY IS NOT SET. Figure 31. AD7143 Proximity Detection and Environmental Calibration Σ-Δ 16 16-BIT CDC Figure 32. AD7143 Maximum and Minimum Level Detection Logic COMPARATOR 1 PROXIMITY 1 |WORD0 TO WORD3| PROXIMITY_DETECTION_RATE REGISTER 0x003 STAGE_FF_AVG COMPARATOR 2 |AVERAGE– ...

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... STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW values based on the threshold sensitivity settings and the ambient value. These values for this example are sufficient to detect a sensor contact, resulting with the AD7143 asserting the INT output when the threshold levels are exceeded. SENSOR 1 INT ASSERTED ...

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... This closed-loop routine ensures the reliability and repeatable operation of every sensor connected to the AD7143 under dynamic environmental conditions. Figure 35 shows a simplified example of how the AD7143 applies the adaptive calibration process resulting in no interrupt errors under changing CDC ambient levels due to environmental conditions. ...

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... Set to 80% of the STAGE_OFFSET_LOW_CLAMP value. Used in Equation 1. An initial value (based on sensor characterization) is programmed into this register at startup. The AD7143 on-chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. Set to 80% of the STAGE_OFFSET_HIGH_CLAMP value. ...

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... This algorithm continu- ously monitors the output levels of each sensor and automatically rescales the threshold levels proportionally to the sensor area covered by the user result, the AD7143 maintains optimal threshold and sensitivity levels for all types of users regardless of their finger sizes. ...

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... The sensor touch interrupt mode is implemented when the host processor requires an interrupt only when a sensor is contacted. Configuring the AD7143 into this mode results in the interrupt being asserted when the user makes contact with the sensor and again when the user lifts off the sensor. The second interrupt is required to alert the host processor that the user is no longer contacting the sensor ...

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... Interrupt asserted when the user contacts a sensor. See Figure 37. Enable for the CIN inputs connected to the CDC positive stage. Enable for the CIN inputs connected to the CDC negative stage. Continuous interrupt at the end of each STAGEx that is enabled. STAGE8 STAGE9 STAGE10 STAGE11 STAGE0 STAGE1 2 AD7143 ...

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... The AD7143 supports the industry standard 2-wire I interface protocol. The two wires associated with the I the SCLK and the SDA inputs. The SDA is an I/O pin that allows both register write and register readback operations. The AD7143 is 2 always a slave device on the I C serial interface bus ...

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... Bit 9 Bit 8 be set to the address of the required internal register. The master performs a write transaction, and writes to the AD7143 to set the address pointer. The master then outputs a repeat start condition LSB to keep control of the bus, or, if this is not possible, ends the write ...

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... REGISTER DATA [D7:D0] DEV DEV ACK AD7143 DEVICE ADDRESS REGISTER DATA [D7:D0] DEV DEV DEV D7 ACK R Timing for Single Register Readback Operation WRITE DATA WRITE DATA HIGH BYTE [15:8] ...

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... Connect the printed circuit board thermal pad to GND. Rev Page Symbol Min D 1 (4-Layer CAPACITIVE SENSOR BOARD CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING Figure 44. Capacitive Sensor Board with Grounded Shield AD7143 Typ Max Unit mm mm 1.0 mm ...

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... AD7143 POWER-UP SEQUENCE When the AD7143 is powered up, the following sequence is recommended when initially developing the AD7143 and Host μC serial interface: 1. Turn on the power supplies to the AD7143. 2. Write to the Bank 2 registers at Address 0x080 through Address 0x0DF. These registers are contiguous sequential register write sequence can be applied. ...

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... SENSOR PCB SDA 12 1 CIN2 VDRIVE 11 2 CIN3 AD7143 3 CIN4 GND 10 4 CIN5 VCC 9 10nF 2 Figure 46. Typical Application Circuit with I C Interface Rev Page AD7143 VDRIVE 2.2kΩ 2.2kΩ 2.2kΩ INT SCLK HOST WITH INTERFACE V SDA HOST OPTIONAL INTERFACE ...

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... These registers automatically update at the end of each conversion sequence. Although these registers are primarily used by the AD7143 internal data processing, they are accessible by the host processor for additional external data processing, if desired. Default values are undefined for Bank 2 registers and Bank 3 registers until after power up and configuration of the Bank 2 registers ...

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... Interrupt polarity control 0 = active low 1 = active high EXCITATION_SOURCE Excitation source control for Pin enable output 1 = disable output Unused Set unused register bits = 0 CDC_BIAS CDC bias current control 00 = normal operation 01 = normal operation + 20 normal operation + 35 normal operation + 50% Rev Page AD7143 ...

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... AD7143 Table 17. STAGE_CAL_EN Register Address Data Bit Default Type 0x001 [0] 0 R/W [1] 0 [2] 0 [3] 0 [4] 0 [5] 0 [6] 0 [7] 0 [11:8] 0 [13:12] 0 [15:14] 0 Name Description STAGE0_CAL_EN STAGE0 calibration enable 0 = disable 1 = enable STAGE1_CAL_EN STAGE1 calibration enable 0 = disable 1 = enable STAGE2_CAL_EN STAGE2 calibration enable 0 = disable 1 = enable STAGE3_CAL_EN STAGE3 calibration enable ...

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... STAGE0 Name Description PROXIMITY_RECAL_LVL Proximity recalibration level PROXIMITY_DETECTION_RATE Proximity detection rate SLOW_FILTER_UPDATE_LVL Slow filter update level Name Description FP_PROXIMITY_RECAL Full power mode proximity recalibration time control LP_PROXIMITY_RECAL Low power mode proximity recalibration time control Rev Page AD7143 ...

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... AD7143 Table 21. STAGE_LOW_INT_EN Register Address Data Bit Default Type 0x005 [0] 0 R/W [1] 0 [2] 0 [3] 0 [4] 0 [5] 0 [6] 0 [7] 0 [11:8] 0 [15:12] 0 Name Description STAGE0_LOW_INT_EN STAGE0 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded STAGE1_LOW_INT_EN STAGE1 low interrupt enable 0 = interrupt source disabled ...

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... INT asserted if STAGE0 high threshold is exceeded STAGE6_HIGH_INT_EN STAGE6 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded STAGE7_HIGH_INT_EN STAGE7 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded Unused Set unused register bits = 0 Rev Page AD7143 ...

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... AD7143 Table 23. STAGE_COMPLETE_INT_EN Register Address Data Bit Default Type 0x007 [0] 0 R/W [1] 0 [2] 0 [3] 0 [4] 0 [5] 0 [6] 0 [7] 0 [11:8] 0 [12] 0 [15:13] Table 24. STAGE_LOW_LIMIT_INT Register Address Data Bit Default Type 0x008 [ [1] 0 [2] 0 [3] 0 [4] 0 [5] 0 [6] 0 [7] 0 [15:8] 1 Registers self-clear to 0 after readback, provided that the limits are not exceeded. ...

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... STAGE0 conversion completed STAGE5_COMPLETE_STATUS_INT STAGE5 conversion complete register interrupt status 1 indicates STAGE0 conversion completed STAGE6_COMPLETE_STATUS_INT STAGE6 conversion complete register interrupt status 1 indicates STAGE0 conversion completed STAGE7_COMPLETE_STATUS_INT STAGE7 conversion complete register interrupt status 1 indicates STAGE0 conversion completed Unused Rev Page AD7143 ...

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... STAGE6 CDC 16-bit conversion data ADC_RESULT_S7 STAGE7 CDC 16-bit conversion data Name Description REVISION_CODE AD7143 revision code DEVID AD7143 device ID = 0xE63 Name Description STAGE0_PROXIMITY_STATUS STAGE0 proximity status register 1 indicates proximity detected on STAGE0 STAGE1_PROXIMITY_STATUS STAGE1 proximity status register 1 indicates proximity detected on STAGE1 ...

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... STAGE2_AFE_OFFSET STAGE2 AFE offset control (see Table 40) STAGE2_SENSITIVITY STAGE2 sensitivity control (see Table 41) STAGE2_OFFSET_LOW STAGE2 initial offset low value STAGE2_OFFSET_HIGH STAGE2 initial offset high value STAGE2_OFFSET_HIGH_CLAMP STAGE2 offset high clamp value STAGE2_OFFSET_LOW_CLAMP STAGE2 offset low clamp value Rev Page AD7143 ...

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... AD7143 Table 33. STAGE3 Configuration Registers Address Data Bit Default Type 0x098 [15:0] X R/W 0x099 [15:0] X R/W 0x09A [15:0] X R/W 0x09B [15:0] X R/W 0x09C [15:0] X R/W 0x09D [15:0] X R/W 0x09E [15:0] X R/W 0x09F [15:0] X R/W Table 34. STAGE4 Configuration Registers Address Data Bit Default Type 0x0A0 [15:0] X R/W 0x0A1 [15:0] X R/W 0x0A2 [15:0] X R/W 0x0A3 [15:0] X R/W 0x0A4 [15:0] X R/W 0x0A5 [15:0] X R/W 0x0A6 [15:0] X R/W 0x0A7 [15:0] X R/W Table 35. STAGE5 Configuration Registers Address Data Bit ...

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... CIN5 connected to CDC positive input 11 = CIN5 connected to BIAS (connect unused CIN inputs) CIN6 connection setup 00 = CIN6 not connected to CDC inputs 01 = CIN6 connected to CDC negative input 10 = CIN6 connected to CDC positive input 11 = CIN6 connected to BIAS (connect unused CIN inputs) Rev Page AD7143 ...

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... AD7143 Table 39. STAGEX Detailed CIN7 Connection Setup Description Data Bit Default Type Name [1:0] X R/W CIN7_CONNECTION_SETUP [13:2] X R/W Unused [14] X R/W NEG_AFE_OFFSET_DISABLE [15] X R/W POS_AFE_OFFSET_DISABLE Table 40. STAGEX Detailed Offset Control Description ( Data Bit Default Type Name [6:0] X R/W NEG_AFE_OFFSET [7] X R/W NEG_AFE_OFFSET_SWAP [14:8] X R/W POS_AFE_OFFSET [15] X R/W POS_AFE_OFFSET_SWAP Table 41. STAGEX Detailed Sensitivity Control Description ( ...

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... STAGE0 minimum value FIFO WORD0 STAGE0_MIN_WORD1 STAGE0 minimum value FIFO WORD1 STAGE0_MIN_WORD2 STAGE0 minimum value FIFO WORD2 STAGE0_MIN_WORD3 STAGE0 minimum value FIFO WORD3 STAGE0_MIN_AVG STAGE0 average minimum FIFO value STAGE0_LOW_THRESHOLD STAGE0 low threshold value STAGE0_MIN_TEMP STAGE0 temporary minimum value Unused Rev Page AD7143 ...

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... AD7143 Table 43. STAGE1 Results Registers Address Data Bit Default Type 0x104 [15:0] X R/W 0x105 [15:0] X R/W 0x106 [15:0] X R/W 0x107 [15:0] X R/W 0x108 [15:0] X R/W 0x109 [15:0] X R/W 0x10A [15:0] X R/W 0x10B [15:0] X R/W 0x10C [15:0] X R/W 0x10D [15:0] X R/W 0x10E [15:0] X R/W 0x10F [15:0] X R/W 0x110 [15:0] X R/W 0x111 [15:0] X R/W 0x112 [15:0] X R/W 0x113 [15:0] X R/W 0x114 [15:0] X R/W 0x115 [15:0] X R/W 0x116 [15:0] X R/W 0x117 [15:0] X R/W 0x118 [15:0] X R/W 0x119 [15:0] X R/W 0x11A [15:0] X R/W 0x11B [15:0] X R/W 0x11C [15:0] X R/W 0x11D [15:0] X R/W 0x11E [15:0] X R/W 0x11F [15:0] X R/W 0x120 [15:0] X R/W 0x121 [15:0] X R/W 0x122 ...

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... STAGE2 minimum value FIFO WORD0 STAGE2_MIN_WORD1 STAGE2 minimum value FIFO WORD1 STAGE2_MIN_WORD2 STAGE2 minimum value FIFO WORD2 STAGE2_MIN_WORD3 STAGE2 minimum value FIFO WORD3 STAGE2_MIN_AVG STAGE2 average minimum FIFO value STAGE2_LOW_THRESHOLD STAGE2 low threshold value STAGE2_MIN_TEMP STAGE2 temporary minimum value Unused Rev Page AD7143 ...

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... AD7143 Table 45. STAGE3 Results Registers Address Data Bit Default Type 0x14C [15:0] X R/W 0x14D [15:0] X R/W 0x14E [15:0] X R/W 0x14F [15:0] X R/W 0x150 [15:0] X R/W 0x151 [15:0] X R/W 0x152 [15:0] X R/W 0x153 [15:0] X R/W 0x154 [15:0] X R/W 0x155 [15:0] X R/W 0x156 [15:0] X R/W 0x157 [15:0] X R/W 0x158 [15:0] X R/W 0x159 [15:0] X R/W 0x15A [15:0] X R/W 0x15B [15:0] X R/W 0x15C [15:0] X R/W 0x15D [15:0] X R/W 0x15E [15:0] X R/W 0x15F [15:0] X R/W 0x160 [15:0] X R/W 0x161 [15:0] X R/W 0x162 [15:0] X R/W 0x163 [15:0] X R/W 0x164 [15:0] X R/W 0x165 [15:0] X R/W 0x166 [15:0] X R/W 0x167 [15:0] X R/W 0x168 [15:0] X R/W 0x169 [15:0] X R/W 0x16A ...

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... STAGE4 minimum value FIFO WORD0 STAGE4_MIN_WORD1 STAGE4 minimum value FIFO WORD1 STAGE4_MIN_WORD2 STAGE4 minimum value FIFO WORD2 STAGE4_MIN_WORD3 STAGE4 minimum value FIFO WORD3 STAGE4_MIN_AVG STAGE4 average minimum FIFO value STAGE4_LOW_THRESHOLD STAGE4 low threshold value STAGE4_MIN_TEMP STAGE4 temporary minimum value Unused Rev Page AD7143 ...

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... AD7143 Table 47. STAGE5 Results Registers Address Data Bit Default Type 0x194 [15:0] X R/W 0x195 [15:0] X R/W 0x196 [15:0] X R/W 0x197 [15:0] X R/W 0x198 [15:0] X R/W 0x199 [15:0] X R/W 0x19A [15:0] X R/W 0x19B [15:0] X R/W 0x19C [15:0] X R/W 0x19D [15:0] X R/W 0x19E [15:0] X R/W 0x19F [15:0] X R/W 0x1A0 [15:0] X R/W 0x1A1 [15:0] X R/W 0x1A2 [15:0] X R/W 0x1A3 [15:0] X R/W 0x1A4 [15:0] X R/W 0x1A5 [15:0] X R/W 0x1A6 [15:0] X R/W 0x1A7 [15:0] X R/W 0x1A8 [15:0] X R/W 0x1A9 [15:0] X R/W 0x1AA [15:0] X R/W 0x1AB [15:0] X R/W 0x1AC [15:0] X R/W 0x1AD [15:0] X R/W 0x1AE [15:0] X R/W 0x1AF [15:0] X R/W 0x1B0 [15:0] X R/W 0x1B1 [15:0] X R/W 0x1B2 ...

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... STAGE6 minimum value FIFO WORD0 STAGE6_MIN_WORD1 STAGE6 minimum value FIFO WORD1 STAGE6_MIN_WORD2 STAGE6 minimum value FIFO WORD2 STAGE6_MIN_WORD3 STAGE6 minimum value FIFO WORD3 STAGE6_MIN_AVG STAGE6 average minimum FIFO value STAGE6_LOW_THRESHOLD STAGE6 low threshold value STAGE6_MIN_TEMP STAGE6 temporary minimum value Unused Rev Page AD7143 ...

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... AD7143 Table 49. STAGE7 Results Registers Address Data Bit Default Type 0x1DC [15:0] X R/W 0x1DD [15:0] X R/W 0x1DE [15:0] X R/W 0x1DF [15:0] X R/W 0x1E0 [15:0] X R/W 0x1E1 [15:0] X R/W 0x1E2 [15:0] X R/W 0x1E3 [15:0] X R/W 0x1E4 [15:0] X R/W 0x1E5 [15:0] X R/W 0x1E6 [15:0] X R/W 0x1E7 [15:0] X R/W 0x1E8 [15:0] X R/W 0x1E9 [15:0] X R/W 0x1EA [15:0] X R/W 0x1EB [15:0] X R/W 0x1EC [15:0] X R/W 0x1ED [15:0] X R/W 0x1EE [15:0] X R/W 0x1EF [15:0] X R/W 0x1F0 [15:0] X R/W 0x1F1 [15:0] X R/W 0x1F2 [15:0] X R/W 0x1F3 [15:0] X R/W 0x1F4 [15:0] X R/W 0x1F5 [15:0] X R/W 0x1F6 [15:0] X R/W 0x1F7 [15:0] X R/W 0x1F8 [15:0] X R/W 0x1F9 [15:0] X R/W 0x1FA ...

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... Figure 48. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ × Very Thin Quad (CP-16-13) Dimensions shown in millimeters Serial Interface Description Interface Interface Interface Rev Page 0.50 0.40 0. 2.65 EXPOSED 2.50 SQ PAD 2. 0.25 MIN Package Description Package Option 16-Lead LFCSP_VQ CP-16-13 16-Lead LFCSP_VQ CP-16-13 Evaluation Board AD7143 ...

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... AD7143 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...