AD7631 Analog Devices, AD7631 Datasheet

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... The device is configured through hardware or via a dedicated write-only serial configuration port for input range and operating mode. The AD7631 contains a high speed 18-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. A falling edge on CNVST samples the fully differential analog inputs on IN+ and IN− ...

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... AD7631 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 12 Terminology .................................................................................... 16 Theory of Operation ...................................................................... 17 Overview...................................................................................... 17 Converter Operation.................................................................. 17 Transfer Functions...................................................................... 18 Typical Connection Diagram ................................................... 18 Analog Inputs.............................................................................. 19 REVISION HISTORY 3/11— ...

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... V = all other input ranges kHz kHz kHz kHz Full-scale step Rev Page AD7631 unless otherwise noted. MIN MAX Min Typ Max Unit 18 Bits − REF REF − REF REF − ...

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... AD7631 Parameter INTERNAL REFERENCE Output Voltage Temperature Drift Line Regulation Long-Term Drift Turn-On Settling Time REFERENCE BUFFER REFBUFIN Input Voltage Range EXTERNAL REFERENCE Voltage Range Current Drain TEMPERATURE PIN Voltage Output Temperature Sensitivity Output Resistance DIGITAL INPUTS Logic Levels ...

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... L Rev Page AD7631 unless otherwise noted. MIN MAX Typ Max Unit ns μ 1.68 μ 1.68 μ 1.65 μ ...

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... AD7631 Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] DIVSCLK[0] SYNC to SDCLK First Edge Delay Minimum Internal SDCLK Period Minimum Internal SDCLK Period Maximum Internal SDCLK High Minimum Internal SDCLK Low Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum ...

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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION = 91°C/W and θ = 30°C/ 26°C/W. JA Rev Page AD7631 ...

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... When MODE[1: this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode AGND 1 PIN 1 AVDD 2 MODE0 3 MODE1 4 D0/OB/2C 5 AD7631 OGND 6 TOP VIEW OGND 7 (Not to Scale) D1/A0 8 D2/ ...

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... When MODE[1: Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated (master) or the external (slave) serial data clock for the AD7631 output data. When EXT/INT = low (master mode), the internal serial data clock is selected on SDCLK output. ...

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... RESET DI Reset Input. When high, reset the AD7631. Current conversion, if any, is aborted. The falling edge of RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register. See the 2 ...

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... In all ranges, IN+ must be driven 180° out of phase with IN−. 45 TEMP AO Temperature Sensor Analog Output. When the internal reference is enabled (PDREF = PDBUF = low), this pin outputs a voltage proportional to the temperature of the AD7631. See the Voltage Reference Input/Output section. 46 REFBUFIN AI Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 2 ...

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... AD7631 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = − 2 250kSPS POSITIVE INL = 1.15 LSB S NEGATIVE INL = –0.94 LSB 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 0 65536 131072 CODE Figure 5. Integral Nonlinearity vs. Code, Bipolar 10 V Range 60 NEGATIVE INL POSITIVE INL ...

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... TO 5V –50 –40 –30 –20 –10 INPUT LEVEL (dB) SFDR SECOND THD HARMONIC THIRD 10 100 FREQUENCY (kHz) ±5V ±10V 0V TO 10V –35 – TEMPERATURE (°C) Figure 16. SINAD vs. Temperature AD7631 SNR SINAD 0 140 120 100 1000 105 125 ...

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... AD7631 –104 –108 –112 –116 ±10V –120 –124 0V TO 10V ±5V –128 –132 –55 –35 – TEMPERATURE (°C) Figure 17. THD vs. Temperature ZERO/OFFSET ERROR –4 –8 –12 NEGATIVE FULL-SCALE ERROR –16 –20 –55 –35 – TEMPERATURE (°C) Figure 18. Zero/Offset Error, Positive and Negative Full-Scale Error vs. Temperature, All Normalized to 25° ...

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... TEMPERATURE (°C) Figure 23. Power-Down Operating Currents vs. Temperature 105 Figure 24. Typical Delay vs. Load Capacitance C Rev Page AD7631 OVDD = 2.7V @ 85°C OVDD = 2.7V @ 25°C OVDD = 5V @ 85°C OVDD = 5V @ 25°C 50 100 150 200 C (pF ...

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... CNVST input to when the input signal is held for a conversion. Transient Response The time required for the AD7631 to achieve its rated accuracy after a full-scale step function is applied to its input. Reference Voltage Temperature Coefficient The reference voltage temperature coefficient is derived from the typical shift of output voltage at 25° ...

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... The AD7631 is a very fast, low power, precise, 18-bit ADC using successive approximation, capacitive digital-to-analog (CDAC) architecture. The AD7631 can be configured at any time for one of four input ranges with inputs in parallel and serial hardware modes dedicated write-only, SPI-compatible interface via a configuration register in serial software mode. The AD7631 uses Analog Devices’ ...

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... This is also the code for underrange analog input. TYPICAL CONNECTION DIAGRAM Figure 27 shows a typical connection diagram for the AD7631 using the internal reference, serial data interface, and serial configuration port. Different circuitry from that shown in Figure 27 is optional and is discussed in the following sections. ...

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... REFBUFIN REFGND AD7631 IN+ IN– NOTE 3 PDREF PDBUF PD RD AGND DGND NOTE 8 Input Structure Figure 28 shows an equivalent circuit for the input structure of the AD7631. IN+ OR IN– Rev Page DIGITAL INTERFACE SUPPLY (2.5V, 3.3V, OR 5V) 10µF OGND MicroConverter MICROPROCESSOR/ BUSY SDCLK SERIAL PORT 1 ...

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... V range. During the conversion phase, when the switches are opened, the input impedance is limited to C Because the input impedance of the AD7631 is very high, it can be directly driven by a low impedance source without gain error. To further improve the noise filtering achieved by the AD7631 analog input circuit, an external, one-pole RC filter between the amplifier’ ...

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... Again, to preserve the SNR of the converter, the resistors R R should be kept low. G VOLTAGE REFERENCE INPUT/OUTPUT The AD7631 allows the choice of either a very low temperature drift internal voltage reference, an external reference external buffered reference. The internal reference of the AD7631 provides excellent performance and can be used in almost all applications. ...

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... Sufficient decoupling of these supplies is required consisting of at least a 10 μF capacitor and a 100 nF capacitor on each supply. The 100 nF capacitors should be placed as close as possible to the AD7631. To reduce the number of supplies needed, the DVDD can be supplied through a simple RC filter from the analog supply, as shown in Figure 27. ...

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... PD input is a don’t care and should be tied to either high or low. CONVERSION CONTROL The AD7631 is controlled by the CNVST input. A falling edge on CNVST is all that is necessary to initiate a conversion. A detailed timing diagram of the conversion process is shown in ...

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... RD is generally used to enable the conversion result on the data bus. RESET The RESET input is used to reset the AD7631. A rising edge on RESET aborts the current conversion (if any) and tristates the data bus. The falling edge of RESET resets the AD7631 and clears the data bus and configuration register ...

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... MODE[1:0]= 3. The AD7631 has a serial interface (SPI-compatible) multiplexed on the data pins D[17:4]. Data Interface The AD7631 outputs 18 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 18 clock pulses provided on the SDCLK pin. The output data is valid on both the rising and falling edge of the data clock ...

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... EXT/ INT , INVSCLK, SDIN, SDOUT, SDCLK, and RDERROR. External Clock (MODE[1: EXT/ INT = High) Setting the EXT/ INT = high allows the AD7631 to accept an externally supplied serial data clock on the SDCLK pin. In this mode, several methods can be used to read the data. The external serial clock is gated by CS ...

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... Daisy-Chain Feature In addition, in the read after convert mode, the AD7631 provides a daisy-chain feature for cascading multiple converters together using the serial data input pin, SDIN. This feature is useful for reducing component count and wiring connections when desired, for instance, in isolated multiconverter applications ...

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... AD7631 CS BUSY t 31 SDCLK X* SDOUT t 16 SDIN *A DISCONTINUOUS SDCLK IS RECOMMENDED. CS CNVST BUSY t 31 SDCLK X* SDOUT DISCONTINUOUS SDCLK IS RECOMMENDED. Figure 45. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) MODE[1: EXT/INT = 1 INVSCLK = ...

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... HARDWARE CONFIGURATION The AD7631 can be configured at any time with the dedicated hardware pins BIPOLAR, TEN, D0/OB and PD for parallel mode (MODE[1: serial hardware mode (MODE[1: HW high). Programming the AD7631 for mode selection and input range configuration can be done before or during conversion. Like the RESET input, the ADC ...

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... Figure 48 shows an interface diagram between the AD7631 and the SPI-equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7631 acts as a slave device, and data must be read after conversion. This mode also allows the daisy-chain feature. The convert command could be initiated in response to an internal timer interrupt ...

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... Digital and analog ground planes should be joined in only one place, preferably underneath the AD7631 close as possible to the AD7631. If the AD7631 system where multiple devices require analog-to-digital ground connections, the connections should still be made at one point only, a star ground point, established as close as possible to the AD7631 ...

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... Model Notes Temperature Range AD7631BCPZ −40°C to +85°C AD7631BCPZRL −40°C to +85°C AD7631BSTZ −40°C to +85°C AD7631BSTZRL −40°C to +85°C 2 EVAL-AD7631CBZ 3 EVAL-CONTROL BRD3 RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. ...