AD9230 Analog Devices, AD9230 Datasheet - Page 24

• Manufacturer Part Number: AD9230
• Description: 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9230

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni
• Ain Range: 1.25 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9230
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 12.
If it is desired to change the output data format to twos comple-
ment, see the AD9230 Configuration Using the SPI section.
An output clock signal is provided to assist in capturing data
from the AD9230. The DCO is used to clock the output data
and is equal to the sampling clock (CLK) rate. In single data rate
mode (SDR), data is clocked out of the AD9230 and must be
captured on the rising edge of the DCO. In double data rate
mode (DDR), data is clocked out of the AD9230 and must be
captured on the rising and falling edges of the DCO See the
timing diagrams shown in Figure 2 and Figure 3 for more
information.
Output Data Rate and Pinout Configuration
The output data of the AD9230 can be configured to drive 12
pairs of LVDS outputs at the same rate as the input clock signal
(single data rate, or SDR, mode), or six pairs of LVDS outputs at
2× the rate of the input clock signal (double data rate, or DDR,
mode). SDR is the default mode; the device may be reconfigured
for DDR by setting Bit 3 in Register 14 (see Table 13).
Out-of-Range (OR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OR has the same
pipeline latency as the digital data. OR is low when the analog
input voltage is within the analog input range and high when
the analog input voltage exceeds the input range, as shown in
Figure 63. OR remains high until the analog input returns to
within the input range and another conversion is completed. By
logically AND-ing OR with the MSB and its complement, over-
range high or underrange low conditions can be detected.
Figure 62. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths
–200
–400
–600
600
400
200
0
–3
Greater than 24 Inches on Standard FR-4, AD9230-250
–2
–1
TIME (ns)
0
1
2
3
12
10
–100
8
6
4
2
0
TIME (ps)
0
100
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TIMING
The AD9230 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one
propagation delay (t
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9230.
These transients can degrade the converter’s dynamic performance.
The AD9230 also provides data clock output (DCO) intended for
capturing the data in an external register. The data outputs are valid
on the rising edge of DCO.
The lowest typical conversion rate of the AD9230 is 40 MSPS.
At clock rates below 1 MSPS, the AD9230 assumes the standby
mode.
RBIAS
The AD9230 requires the user to place a 10 kΩ resistor between
the RBIAS pin and ground. This resister should have a 1%
tolerance and is used to set the master current reference of the
ADC core.
AD9230 CONFIGURATION USING THE SPI
The AD9230 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space inside the ADC. This gives the user added flexibility to
customize device operation depending on the application.
Addresses are accessed (programmed or readback) serially in
one-byte words. Each byte may be further divided down into
fields, which are documented in the Memory Map section.
There are three pins that define the serial port interface or SPI
to this particular ADC. They are the SPI SCLK/DFS, SPI
SDIO/DCS, and CSB pins. The SCLK/DFS (serial clock) is used
to synchronize the read and write data presented the ADC. The
SDIO/DCS (serial data input/output) is a dual-purpose pin that
allows data to be sent and read from the internal ADC memory
map registers. The CSB is an active low control that enables or
disables the read and write cycles (see Table 9).
OR DATA OUTPUTS
1
0
0
0
0
1
Figure 63. OR Relation to Input Voltage and Output Data
1111
1111
1111
0000
0000
0000
1111
1111
1111
0000
0000
0000
1111
1111
1110
0001
0000
0000
PD
) after the rising edge of the clock signal.
–FS – 1/2 LSB
OR
–FS
–FS + 1/2 LSB
+FS – 1/2 LSB
+FS – 1 LSB
+FS