AD7622 Analog Devices, AD7622 Datasheet - Page 9

• Manufacturer Part Number: AD7622
• Manufacturer: Analog Devices

Specifications of AD7622

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 2MSPS
• Interface: Byte,Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

Pin
No.
14
15
16
17
18
19
20
21
22
23
24
25 to
28
29
30
Mnemonic
D5
or INVSYNC
D6
or INVSCLK
D7
or RDC
or SDIN
OGND
OVDD
DVDD
DGND
D8
or SDOUT
D9
or SCLK
D10
or SYNC
D11
or RDERROR
D[12:15]
BUSY
DGND
Type
DI/O
DI/O
DI/O
P
P
P
P
DO
DI/O
DO
DO
DO
DO
P
1
Description
When SER/PAR = low, this output is used as Bit 5 of the parallel port data output bus.
When SER/PAR = high, invert sync select. In serial master mode (EXT/INT = low), this input is used
to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
When SER/PAR = low, this output is used as Bit 6 of the parallel port data output bus.
When SER/PAR] = high, invert SCLK select. In all serial modes, this input is used to
invert the SCLK signal.
When SER/PAR = low, this output is used as bit 7 of the parallel port data output bus.
When SER/PAR = high, read during convert. When using serial master mode (EXT/INT = low),
RDC is used to select the read mode.
When RDC = high, the previous conversion result is output on SDOUT during conversion and
the period of SCLK changes (see the Master Serial Interface section).
When RDC = low (read after convert), the current result can be output on SDOUT only when
the conversion is complete.
When SER/PAR = low, serial data in. When using serial slave mode, (EXT/INT = high), SDIN could be
used as a data input to daisy-chain the conversion results from two or more ADCs onto a single
SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SCLK periods after
the initiation of the read sequence. If not used, connect to OVDD or OGND.
Input/Output Interface Digital Power Ground.
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the
host interface (2.5 V or 3 V).
Digital Power. Nominally at 2.5 V.
Digital Power Ground.
When SER/PAR = low, this output is used as Bit 8 of the parallel port data output bus.
When SER/PAR = high, serial data output. In serial mode, this pin is used as the serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7622 provides the
conversion result, MSB first, from its internal shift register. The data format is determined by the logic
level of OB/2C.
In master mode, EXT/INT = low, SDOUT is valid on both edges of SCLK.
In slave mode, EXT/INT = high:
When SER/PAR = low, this output is used as Bit 9 of the parallel port data output bus.
When SER/PAR = high, serial clock. In all serial modes, this pin is used as the serial
data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge
where the data SDOUT is updated, depends on the logic state of the INVSCLK pin.
When SER/PAR = low, this output is used as Bit 10 of the parallel port data output bus.
When SER/PAR = high, frame synchronization. In serial master mode (EXT/INT= low),
this output is used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high
while SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low
while SDOUT output is valid.
When SER/PAR = low, this output is used as Bit 11 of the parallel port data output bus.
When SER/PAR = high, read error. In serial slave mode (EXT/INT = high), this output
is used as an incomplete read error flag. If a data read is started and not completed when the
current conversion is complete, the current data is lost and RDERROR is pulsed high.
Bit 12 to Bit 15 of the parallel port data output bus. These pins are always outputs, regardless of
the interface mode.
Busy Output. Transitions high when a conversion is started and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal.
Digital Power Ground.
When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
Rev. 0 | Page 9 of 28
AD7622
2
2