AD7690 Analog Devices, AD7690 Datasheet - Page 20

• Manufacturer Part Number: AD7690
• Manufacturer: Analog Devices

Specifications of AD7690

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 400kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7690
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7690 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the analog
input, independent of the signal used to select the data reading.
This independence is particularly important in applications where
low jitter on CNV is desired.
The connection diagram is shown in Figure 40, and the
corresponding timing is given in Figure 41.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
ACQUISITION
SDO
CNV
SCK
SDI
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
Figure 41. 4-Wire CS Mode with Busy Indicator Serial Interface Timing
Figure 40. 4-Wire CS Mode with Busy Indicator Connection Diagram
t
EN
SDI
AD7690
CNV
SCK
1
Rev. B | Page 20 of 24
t
t
HSDO
DSDO
SDO
D17
2
VIO
t
47kΩ
CYC
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7690
then enters the acquisition phase and powers down. The data
bits are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 19
SDI going high (whichever occurs first), SDO returns to high
impedance.
D16
3
ACQUISITION
CLK
CS1
CONVERT
DATA IN
IRQ
DIGITAL HOST
t
ACQ
t
SCKL
t
SCKH
17
t
SCK
18
D1
19
D0
t
DIS
th
SCK falling edge or