AD7323 Analog Devices, AD7323 Datasheet - Page 24

• Manufacturer Part Number: AD7323
• Description: 500 kSPS, 4-Channel, Software Selectable True bipolar Input, 12-Bit Plus Sign A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7323

• Resolution (bits): 13bit
• # Chan: 4
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: Bip 10V,Bip 2.5V,Bip 5.0V,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

AD7323
Table 11. Power Mode Selection
PM1
1
1
0
0
Table 12. Sequencer Selection
Seq1
0
0
1
1
PM0
1
0
1
0
Seq2
0
1
0
1
Description
Full shutdown mode. In this mode, all internal circuitry on the AD7323 is powered down. Information in the control register
is retained when the AD7323 is in full shutdown mode.
Autoshutdown mode. The AD7323 enters autoshutdown on the 15
All internal circuitry is powered down in autoshutdown.
Autostandby mode. In this mode, all internal circuitry is powered down, excluding the internal reference. The AD7323 enters
autostandby mode on the 15
Normal mode. All internal circuitry is powered up at all times.
Description
The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the
control register, selects the next channel for conversion.
Uses the sequence of channels previously programmed into the sequence register for conversion. The AD7323 starts
converting on the lowest channel in the sequence. The channels are converted in ascending order. If uninterrupted, the
AD7323 keeps converting the sequence. The range for each channel defaults to the range previously written into the range
register.
Used in conjunction with the channel address bits in the control register. This allows continuous conversions on a
consecutive sequence of channels, from Channel 0 through a final channel selected by the channel address bits in the
control register. The range for each channel defaults to the range previously written into the range register.
The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the
control register, selects the next channel for conversion.
th
SCLK rising edge after the control register is updated.
Rev. A | Page 24 of 36
th
SCLK rising edge when the control register is updated.