AD7273 Analog Devices, AD7273 Datasheet
AD7273
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AD7273 Summary of contents
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... Power-down mode: 0.1 μA typ 8-lead TSOT package 8-lead MSOP package GENERAL DESCRIPTION The AD7273/AD7274 are 10-/12-bit, high speed, low power, successive approximation ADCs, respectively. The parts operate from a single 2. 3.6 V power supply and feature throughput rates MSPS. Each part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 55 MHz ...
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... Typical Connection Diagram ....................................................... 16 Analog Input ............................................................................... 16 Digital Inputs .............................................................................. 16 Modes of Operation ....................................................................... 17 Normal Mode.............................................................................. 17 Partial Power-Down Mode ....................................................... 17 Full Power-Down Mode ............................................................ 17 Power-Up Times......................................................................... 18 Power vs. Throughput Rate....................................................... 20 Serial Interface ................................................................................ 21 Microprocessor Interfacing....................................................... 23 Application Hints ........................................................................... 24 Grounding and Layout .............................................................. 24 Evaluating the AD7273/AD7274 Performance......................... 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25 Rev Page ...
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... V − 0.2 V min DD 0.2 V max ±2.5 μA max 4.5 pF max Straight (natural) binary Rev Page AD7273/AD7274 = unless otherwise noted. MIN MAX Test Conditions/Comments MHz sine wave MHz 0.97 MHz MHz 0.97 MHz @ 0.1 dB Guaranteed no missed codes to 12 bits − ...
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... AD7273/AD7274 Parameter CONVERSION RATE Conversion Time 3 Track-and-Hold Acquisition Time Throughput Rate POWER RQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) 5 Power Dissipation Normal Mode (Operational) Partial Power-Down Full Power-Down 1 Temperature range from −40°C to +125°C. ...
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... AD7273 SPECIFICATIONS REF Table 3. Parameter DYNAMIC PERFORMANCE 3 Signal-to-Noise + Distortion (SINAD) 3 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Power Supply Rejection Ratio (PSRR) ...
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... AD7273/AD7274 Parameter POWER RQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) 5 Power Dissipation Normal Mode (Operational) Partial Power-Down Full Power-Down 1 Temperature range from −40°C to +125°C. 2 Typical specifications are tested with V ...
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... SCLK falling edge to SDATA three-state ns max CS rising edge to SDATA three-state μs max Power-up time from full power-down or V voltage SDATA V IL Rev Page AD7273/AD7274 1 Guaranteed by characterization. All input signals t 8 SCLK Figure 4. SCLK Falling Edge SDATA Three-State 1.4V ...
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... AD7273/AD7274 TIMING EXAMPLES For the AD7274 brought high during the 14 rising edge after the two leading zeros and 12 bits of the conversion are provided, the part can achieve the fastest throughput rate, 3 MSPS brought high during the 16 SCLK rising edge after the two leading zeros, 12 bits of the conversion, and two trailing zeros are provided, a throughput rate of 2 ...
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... Exposure to absolute −0 0 maximum rating conditions for extended periods may affect 1 ±10 mA device reliability. −40°C to +125°C −65°C to +150°C 150°C 230°C/W 92°C/W 205.9°C/W 43.74°C/W 255°C 260°C 1.5 kV Rev Page AD7273/AD7274 ...
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... SDATA Data Out. Logic output. The conversion result from the AD7273/AD7274 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7274 consists of two leading zeros followed by the 12 bits of conversion data and two trailing zeros, provided MSB first ...
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... FREQUENCY (kHz) Figure 10. AD7274 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz 16384 POINT FFT – 3MSPS SAMPLE F = 1MHz IN SINAD = 66.56 THD = –77.4 –40 SFDR = –78.2 –60 –80 –100 –120 FREQUENCY (kHz) Figure 11. AD7273 Dynamic Performance at 3 MSP, Input Tone = 1 MHz 72.2 72.0 71.8 71.6 71.4 71.2 71.0 70.8 70.6 70.4 70.2 70.0 69.8 69.6 69.4 69.2 69.0 100 INPUT FREQUENCY (kHz) Figure 12 ...
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... AD7273/AD7274 –70 –80 –90 –100 100mV p-p SINE WAVE DECOUPLING –110 0 500 1000 1500 SUPPLY RIPPLE FREQUENCY (MHz) Figure 16. Power Supply Rejection Ratio (PSRR) vs. Supply Ripple Frequency Without Decoupling 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 500 1000 1500 2000 2500 CODES Figure 17 ...
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... CODES 16000 14000 12000 10000 8000 6000 4000 2000 0 2045 2046 2047 2048 CODE Figure 22. Histogram of Codes for 30,000 Samples 12.0 11.5 11.0 10.5 10.0 2049 2050 1.4 Rev Page AD7273/AD7274 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 V (V) REF Figure 23. ENOB/SINAD vs. Reference Voltage 3.6 ...
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... TERMINOLOGY Integral Nonlinearity (INL) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7273/ AD7274, the endpoints of the transfer function are zero scale at 0.5 LSB below the first code transition and full scale at 0.5 LSB above the last code transition. ...
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... An external reference in the range of 1 REF V is required by the ADC. DD The AD7273/AD7274 also feature a power-down option to save power between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section. CONVERTER OPERATION The AD7273/AD7274 are successive approximation ADCs based on a charge redistribution DAC ...
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... Figure 27. AD7273/AD7274 Typical Connection Diagram ANALOG INPUT Figure 28 shows an equivalent circuit of the analog input structure of the AD7273/AD7274. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mV. Signals exceeding this value cause these diodes to become forward biased and to start conducting current into the substrate ...
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... MODES OF OPERATION The mode of operation of the AD7273/AD7274 is selected by controlling the logic state of the CS signal during a conversion. There are three possible modes of operation: normal mode, partial power-down mode, and full power-down mode. The point at which CS is pulled high after the conversion is initiated determines which power-down mode, if any, the device enters ...
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... SCLK as long as edge is received after the falling edge This is shown as Point A in Figure 31. When power supplies are first applied to the AD7273/AD7274, the ADC can power up in either of the power-down modes or in normal mode. Because of this best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion ...
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... Figure 31. Exiting Partial Power-Down Mode THE PART BEGINS TO POWER VALID DATA Figure 32. Entering Full Power-Down Mode THE PART IS FULLY POWERED Figure 33. Exiting Full Power-Down Mode Rev Page AD7273/AD7274 16 16 VALID DATA THE PART ENTERS FULL POWER DOWN 10 16 THREE-STATE 1 6 VALID DATA ...
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... V). If the power-up time is one dummy DD cycle, that is, 333 ns, and the remaining conversion time is 290 ns, the AD7273/AD7274 can be said to dissipate 11.6 mW for 623 ns during each conversion cycle. If the throughput rate is 200 kSPS, the cycle time is 5 μs and the average power dissipated during each cycle is 623/5,000 × ...
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... Figure 38 at Point B. If the rising edge of CS occurs before 12 SCLKs elapse, the conversion is terminated and the SDATA line goes back into three-state SCLKs are considered in the cycle, the AD7273 clocks out four trailing zeros for the last four bits and SDATA returns to three-state on th the 16 SCLK falling edge, as shown in Figure 38 ...
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... Figure 37. AD7274 Serial Interface Timing Diagram 16 SCLK Cycle t CONVERT DB8 DB1 DB0 ZERO 1/THROUGHPUT Figure 38. AD7273 Serial Interface Timing Diagram Rev Page QUIET ZERO ZERO THREE-STATE TWO TRAILING ZEROS ...
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... MICROPROCESSOR INTERFACING AD7273/AD7274 to ADSP-BF53x The ADSP-BF53x family of DSPs interfaces directly to the AD7273/AD7274 without requiring glue logic. The SPORT0 Receive Configuration 1 register should be set up as outlined in Table 8. AD7273/ AD7274 1 SPORT0 SCLK RCLK0 DOUT DR0PRI CS RFS0 DIN DT0 1 ADDITIONAL PINS OMITTED FOR CLARITY Figure 39 ...
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... To provide optimum shielding for ground planes, a minimum etch technique is generally best. All AGND pins of the AD7273/ AD7274 should be sunk into the AGND plane. Digital and analog ground planes should be joined in only one place. If the ...
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... This board is a complete unit that allows control and communicate with all Analog Devices evaluation boards that end designator. To order a complete evaluation kit, the particular ADC evaluation board (such as EVAL-AD7273CB/AD7274CB), the EVAL-CONTROL BRD2, and transformer must be ordered. See the relevant evaluation board technical note for more information ...
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... AD7273/AD7274 NOTES Rev Page ...
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... NOTES Rev Page AD7273/AD7274 ...
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... AD7273/AD7274 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04973–0–9/05(0) T Rev Page ...