AD7763 Analog Devices, AD7763 Datasheet - Page 14

• Manufacturer Part Number: AD7763
• Description: 24-Bit, 625 kSPS, 109 dB Sigma-Delta ADC with On-Chip Buffers, Serial Interface
• Manufacturer: Analog Devices

Specifications of AD7763

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 40MSPS
• Interface: I2S,Ser
• Analog Input Type: Diff-Bip
• Ain Range: 4 V p-p,6.5 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

AD7763
THEORY OF OPERATION
The AD7763 employs a Σ-Δ conversion technique to convert
the analog input into an equivalent digital word. The modulator
samples the input waveform and outputs an equivalent digital
word to the digital filter at a rate equal to ICLK.
Due to the high oversampling rate, which spreads the quanti-
zation noise from 0 to f
band of interest is reduced (see Figure 23). To further reduce
quantization noise, a high order modulator is employed to shape
the noise spectrum; thus, most of the noise energy is shifted out
of the band of interest (see Figure 24).
The digital filtering that follows the modulator removes the
large out-of-band quantization noise (see Figure 25), while
also reducing the data rate from f
to f
decimation rate used.
Digital filtering has certain advantages over analog filtering.
It does not introduce significant noise or distortion and can
be made perfectly linear phase.
The AD7763 employs three finite impulse response (FIR) filters
in series. By using different combinations of decimation ratios
and filter selection, data can be obtained from the AD7763 at
four different data rates. The first filter receives data from the
modulator at ICLK
data at (ICLK/4)
Table 6. Configuration With Default Filter
ICLK
Frequency
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
12.288 MHz
12.288 MHz
12.288 MHz
12.288 MHz
ICLK
/32 or less at the output of the filter, depending on the
MHz
Filter
1
4×
4×
4×
4×
4×
4×
4×
4×
4×
4×
4×
MHz,
.
ICLK
, the noise energy contained in the
where it is decimated × 4 to output
16×
32×
32×
Filter
2
4×
8×
8×
16×
8×
16×
32×
32×
ICLK
Filter 3
2×
Bypassed
2×
Bypassed
2×
Bypassed
2×
2×
2×
Bypassed
2×
at the input of the filter
Data State
Fully filtered
Partially
filtered
Fully filtered
Partially
filtered
Fully filtered
Partially
filtered
Fully filtered
Fully filtered
Fully filtered
Partially
filtered
Fully filtered
Rev. A | Page 14 of 32
Computation
Delay
2.6 μs
4.175 μs
7.325 μs
11.92 μs
1.775 μs
2.25 μs
3.1 μs
4.65 μs
3.66 μs
5.05 μs
7.57 μs
The second filter allows the decimation rate to be chosen from
8× to 32×. The third filter has a fixed decimation rate of 2x, is
user programmable, and has a default configuration (see the
Programmable FIR Filter section). This filter can be bypassed.
Table 6 shows some characteristics of the default filter. The group
delay of the filter is defined as the delay to the center of the
impulse response and is equal to the computation plus filter
delays. The delay until valid data is available (the DVALID status bit
is set) is equal to 2× the filter delay plus the computation delay.
BAND OF INTEREST
BAND OF INTEREST
BAND OF INTEREST
Figure 25. Σ-Δ ADC, Digital Filter Cutoff Frequency
Filter
Delay
44.4 μs
10.8 μs
87.6 μs
20.4 μs
174 μs
39.6 μs
346.8 μs
142.6 μs
283.2 μs
64.45 μs
564.5 μs
Figure 23. Σ-Δ ADC, Quantization Noise
Figure 24. Σ-Δ ADC, Noise Shaping
DIGITAL FILTER CUTOFF FREQUENCY
NOISE SHAPING
QUANTIZATION NOISE
Pass Band
Bandwidth
250 kHz
140.625 kHz
125 kHz
70.3125 kHz
62.5 kHz
35.156 kHz
31.25 kHz
76.8 kHz
38.4 kHz
21.6 kHz
19.2 kHz
Output Data Rate
(ODR)
625 kHz
625 kHz
312.5 kHz
312.5 kHz
156.25 kHz
156.25 kHz
78.125 kHz
192 kHz
96 kHz
96 kHz
48 kHz
f
f
f
ICLK
ICLK
ICLK
/2
/2
/2