AD7277 Analog Devices, AD7277 Datasheet - Page 10

• Manufacturer Part Number: AD7277
• Description: 3 MSPS,10-Bit ADC in 6-Lead TSOT
• Manufacturer: Analog Devices

Specifications of AD7277

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 3MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

AD7276/AD7277/AD7278
TIMING EXAMPLES
For the AD7276, if CS is brought high during the 14
edge after the two leading zeros and 12 bits of the conversion
have been provided, the part can achieve the fastest throughput
rate, 3 MSPS. If CS is brought high during the 16
edge after the two leading zeros and 12 bits of the conversion
and two trailing zeros have been provided, a throughput rate of
2.97 MSPS is achievable. This is illustrated in the following two
timing examples.
Timing Example 1
In Figure 6, using a 14 SCLK cycle, f
throughput is 3 MSPS. This produces a cycle time of t
12.5(1/f
t
ACQ
= 67 ns.
SCLK
) + t
SDATA
ACQ
SCLK
SCLK
SDATA
CS
CS
SCLK
= 333 ns, where t
THREE-
CS
STATE
THREE-
STATE
t
t
2
2
2 LEADING
Z
ZEROS
1
1
t
t
3
ZERO
2
Z
2 LEADING
t
3
ZEROS
1
SCLK
2
ZERO
2
= 6 ns minimum and
2
DB11
= 48 MHz and the
2
t
CONVERT
3
DB11
3
DB10
12.5(1/f
Figure 6. AD7276 Serial Interface Timing 14 SCLK Cycle
Figure 7. AD7276 Serial Interface Timing 16 SCLK Cycle
t
CONVERT
Figure 5. AD7276 Serial Interface Timing Diagram
th
th
3
SCLK rising
4
SCLK
4
SCLK rising
DB10
DB9
2
t
t
t
)
+
6
4
CONVERT
5
4
5
DB9
Rev. C | Page 10 of 28
t
t
4
6
12
1/THROUGHPUT
1/THROUGHPUT
5
DB1
t
7
t
7
13
13
1/THROUGHPUT
B
This satisfies the requirement of 60 ns for t
shows that t
t
the minimum requirement of 4 ns.
Timing Example 2
The example in Figure 7 uses a 16 SCLK cycle, f
and the throughput is 2.97 MSPS. This produces a cycle time of
t
t
t
requirement of 4 ns for t
B
DB0
8
2
ACQ
QUIET
DB1
= 14 ns max. This allows a value of 43 ns for t
+ 12.5(1/f
= 70 ns. Figure 7 shows that t
14
, where t
14
t
5
13
ZERO
t
5
B
2 TRAILING
DB0
ZEROS
15
ACQ
SCLK
15
t
8
8
ZERO
= 14 ns max. This satisfies the minimum
t
14
) + t
8
comprises 0.5(1/f
t
t
9
ACQUISITION
16
ACQ
16
= 336 ns, where t
THREE-STATE
THREE-STATE
QUIET.
t
QUIET
t
1
t
t
QUIET
QUIET
SCLK
ACQ
t
t
1
1
) + t
comprises 2.5(1/f
2
8
= 6 ns minimum and
+ t
ACQ
QUIET
. Figure 6 also
QUIET
SCLK
, where
= 48 MHz,
, satisfying
SCLK
) + t
8
+