AD7688 Analog Devices, AD7688 Datasheet

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AD7688

Manufacturer Part Number
AD7688
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD7688

Resolution (bits)
16bit
# Chan
1
Sample Rate
500kSPS
Interface
Ser,SPI
Analog Input Type
Diff-Uni
Ain Range
(2Vref) p-p
Adc Architecture
SAR
Pkg Type
CSP,SOP

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FEATURES
16-bit resolution with no missing codes
Throughput: 500 kSPS
INL: ±0.4 LSB typ, ±1.5 LSB max (±23 ppm of FSR)
Dynamic range: 96.5 dB
SNR: 95.5 dB @ 20 kHz
THD: −118 dB @ 20 kHz
True differential analog input range
No pipeline delay
Single-supply 5 V operation with
Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible
Daisy-chain multiple ADCs and BUSY indicator
Power dissipation
Standby current: 1 nA
10-lead MSOP (MSOP-8 size) and
Pin-for-pin compatible with AD7685, AD7686, and AD7687
APPLICATIONS
Battery-powered equipment
Data acquisitions
Instrumentation
Medical instruments
Process controls
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
±V
0 V to V
1.8 V/2.5 V/3 V/5 V logic interface
3.75 mW @ 5 V/100 kSPS
3.75 μW @ 5 V/100 SPS
3 mm × 3 mm QFN (LFCSP) (SOT-23 size)
REF
–0.5
–1.0
–1.5
1.5
1.0
0.5
0
0
REF
with V
Figure 1. Integral Nonlinearity vs. Code
REF
16384
up to VDD on both inputs
32768
CODE
POSITIVE INL = +0.31LSB
NEGATIVE INL = –0.39LSB
49152
16-Bit, 1.5 LSB INL, 500 kSPS PulSAR™
65535
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Table 1. MSOP, QFN (LFCSP)/SOT-23 16-Bit PulSAR ADC
Type
True Differential
Pseudo
Differential/Unipolar
Unipolar
GENERAL DESCRIPTION
The AD7688 is a 16-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single 5 V power supply, VDD. It contains a low power,
high speed, 16-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
it samples the voltage difference between IN+ and IN− pins.
The voltages on these pins usually swing in opposite phase
between 0 V and REF. The reference voltage, REF, is applied
externally and can be set up to the supply voltage.
Its power scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus and provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate
supply VIO.
The AD7688 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
VREF
VREF
Differential ADC in MSOP/QFN
0
0
APPLICATION DIAGRAM
©2007–2011 Analog Devices, Inc. All rights reserved.
0.5V TO 5V
IN+
IN–
AD7688
GND
REF
100 kSPS
AD7684
AD7683
AD7680
VDD
Figure 2.
5V
SDO
SCK
CNV
VIO
SDI
250 kSPS
AD7687
AD7685
AD7694
1.8V TO VDD
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
AD7688
www.analog.com
500 kSPS
AD7688
AD7686

Related parts for AD7688

AD7688 Summary of contents

Page 1

... SDI input, to daisy-chain several ADCs on a single, 3-wire bus and provides an optional BUSY indicator compatible with 1 logic, using the separate supply VIO. The AD7688 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C. 49152 65535 One Technology Way, P ...

Page 2

... CS Mode 4-Wire with BUSY Indicator ................................... 20   Chain Mode, No BUSY Indicator ............................................ 21   Chain Mode with BUSY Indicator........................................... 22   Application Hints ........................................................................... 23   Layout .......................................................................................... 23   Evaluating the AD7688’s Performance.................................... 23   Outline Dimensions ....................................................................... 24   Ordering Guide .......................................................................... 25 Rev Page           ...

Page 3

... REF kHz REF kHz kHz kHz REF kHz −60 dB input IN REF Rev Page AD7688 Min Typ Max Unit 16 Bits − REF REF −0 0.1 V REF 0.1 V REF ...

Page 4

... AD7688 VDD = 4 5.5 V, VIO = 2 VDD, V Table 3. Parameter Conditions REFERENCE Voltage Range Load Current 500 kSPS, REF = 5 V SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay VDD = 5 V DIGITAL INPUTS Logic Levels DIGITAL OUTPUTS Data Format Pipeline Delay ...

Page 5

... CYC t CNVH t SCK t SCK t SCKL t SCKH t HSDO t DSDO DIS t SSDICNV t HSDICNV t SSCKCNV t HSCKCNV t SSDISCK t HSDISCK t DSDOSDI Rev Page AD7688 Min Typ Max Unit 0.5 1.6 μs 400 ns 2 μ ...

Page 6

... AD7688 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Analog Inputs 1 1 IN+ , IN− GND − 0 VDD + 0 ±130 mA REF GND − 0 VDD + 0.3 V Supply Voltages VDD, VIO to GND −0 VDD to VIO ±7 V Digital Inputs to GND −0 VIO + 0.3 V Digital Outputs to GND − ...

Page 7

... Rev Page REF 1 10 VIO VDD 2 9 SDI AD7688 IN SCK TOP VIEW (Not to Scale) IN– SDO GND 5 6 CNV NOTES 1. FOR THE LFCSP PACKAGE ONLY, THE EXPOSED PADDLE MUST BE CONNECTED TO GND. Figure 6. 10-Lead QFN (LFCSP) Pin Configuration AD7688 ...

Page 8

... AD7688 TERMINOLOGY Integral Nonlinearity Error (INL) It refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition ...

Page 9

... NEGATIVE DNL = –0.21LSB 0 0 16384 32768 CODE Figure 10. Differential Nonlinearity vs. Code 136187 124933 CODE IN HEX Figure 11. Histogram Input at the Code Transition –10 –8 –6 –4 INPUT LEVEL (dB) Figure 12. SNR vs. Input Level AD7688 49152 65535 VDD = REF = –2 0 ...

Page 10

... AD7688 100 95 ENOB 2.3 2.7 3.1 3.5 3.9 4.3 REFERENCE VOLTAGE (V) Figure 13. SNR, S/(N + D), and ENOB vs. Reference Voltage 100 –55 –35 – TEMPERATURE (°C) Figure 14. SNR vs. Temperature 100 VREF = 5V, –10dB VREF = 5V, –1dB 100 FREQUENCY (kHz) Figure 15. S/( vs. Frequency 17.0 –100 –105 SNR 16 ...

Page 11

... Rev Page GAIN ERROR OFFSET ERROR –35 – TEMPERATURE (°C) Figure 22. Offset and Gain Error vs. Temperature VDD = 5V, 85°C VDD = 5V, 25° 100 SDO CAPACITIVE LOAD (pF) Delay vs. Capacitance Load and Supply DSDO AD7688 105 125 120 ...

Page 12

... The AD7688 is specified from 4 5.5 V and can be interfaced to any of the 1 digital logic family housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines space savings and allows flexible configurations ...

Page 13

... Transfer Functions The ideal transfer characteristic for the AD7688 is shown in Figure 25 and Table 8. 011...111 011...110 011...101 100...010 100...001 100...000 –FSR –FSR + 1 LSB –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT Figure 25. ADC Ideal Transfer Function Table 8. Output Codes and Ideal Input Voltages ...

Page 14

... When the source impedance of the driving circuit is low, the AD7688 can be driven directly. Large source impedances significantly affect the ac performance, especially total harmonic distortion (THD). The dc performances are less sensitive to the input impedance ...

Page 15

... REF and GND pins. POWER SUPPLY The AD7688 is specified has, unlike other low voltage converters, a low enough noise to design a 16-bit resolution system with low supply and respectable performance. It uses two power supply pins: a core supply VDD and a digital input/output interface supply VIO ...

Page 16

... Though the AD7688 has a reduced number of pins, it offers flexibility in its serial interface modes. The AD7688, when in CS mode, is compatible with SPI, QSPI, digital hosts, and DSPs, e.g., Blackfin® ADSP-BF53x or ADSP- 219x. This interface can use either 3-wire or 4-wire. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications ...

Page 17

... CS MODE 3-WIRE, NO BUSY INDICATOR This mode is usually used when a single AD7688 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 34 and the corresponding timing is given in Figure 35. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance ...

Page 18

... AD7688 CS MODE 3-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7688 is connected to an SPI-compatible digital host having an interrupt input. The connection diagram is shown in Figure 36 and the corresponding timing is given in Figure 37. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance ...

Page 19

... Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time. After the 16th SCK falling edge, or when SDI goes high, whichever is earlier, SDO returns to high impedance and another AD7688 can be read. CNV AD7688 SDO ...

Page 20

... AD7688 CS MODE 4-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7688 is connected to an SPI-compatible digital host, which has an interrupt input, and it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This requirement is particularly important in applications where low jitter on CNV is desired ...

Page 21

... CHAIN MODE, NO BUSY INDICATOR This mode can be used to daisy-chain multiple AD7688s wire serial interface. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. ...

Page 22

... SCK falling edge allows a faster reading rate and consequently more AD7688s in the chain, provided the digital host has an acceptable hold time. For instance, with digital host setup time and 3 V interface four AD7688s running at a conversion rate of 360 kSPS can be daisy-chained to a single 3-wire port. ...

Page 23

... The pinout of the AD7688, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7688 is used as a shield ...

Page 24

... AD7688 OUTLINE DIMENSIONS IDENTIFIER PIN 1 INDEX AREA 0.80 0.75 0.70 SEATING PLANE 3.10 3.00 2.90 5. 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.15 0.23 6° 0.30 0.05 0.13 0° 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 48.10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 3.10 3.00 SQ 2.90 6 0.50 0.40 0.30 5 TOP VIEW BOTTOM VIEW 0.05 MAX 0.02 NOM 0.30 0.20 REF ...

Page 25

... Z = RoHS Compliant Part, # denotes RoHS compliant product, may be top or bottom marked. 2 The EVAL-AD7688CB can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. 3 The EVAL-CONTROL BRD2 and EVAL-CONTROL BRD3 allow control and communicate with all Analog Devices evaluation boards ending in the CB designators. ...

Page 26

... AD7688 NOTES Rev Page ...

Page 27

... NOTES Rev Page AD7688 ...

Page 28

... AD7688 NOTES ©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02973-0-2/11(A) Rev Page ...

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