AD7933 Analog Devices, AD7933 Datasheet - Page 18
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AD7933
Manufacturer Part Number
AD7933
Description
4-Channel, 1.5 MSPS, 10-Bit Parallel ADC with a Sequencer
Manufacturer
Analog Devices
Datasheet
1.AD7933.pdf
(32 pages)
Specifications of AD7933
Resolution (bits)
10bit
# Chan
4
Sample Rate
1.5MSPS
Interface
Byte,Par
Analog Input Type
Diff-Uni,SE-Uni
Ain Range
(2Vref) p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
Adc Architecture
SAR
Pkg Type
SOP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7933BRUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD7933/AD7934
TYPICAL CONNECTION DIAGRAM
Figure 18 shows a typical connection diagram for the
AD7933/AD7934. The AGND and DGND pins are connected
together at the device for good noise suppression. If the internal
reference is used, the V
with a 0.47 μF capacitor to avoid noise pickup. Alternatively,
V
In this case, decouple the reference pin with a 0.1 μF capacitor.
In both cases, the analog input range can either be 0 V to V
(RANGE bit = 0) or 0 V to 2 × V
analog input configuration can be either four single-ended
inputs, two differential pairs, or two pseudo differential pairs
(see Table 10). The V
supply. The voltage applied to the V
voltage of the digital interface. As shown in Figure 18, it is
connected to the same 3 V supply of the microprocessor to
allow a 3 V logic interface (see the Digital Inputs section).
0 TO 2 × V
REFIN
0 TO V
V
2.5V
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
/V
REF
with Twos Complement Output Coding and 2 × V
REFOUT
Figure 17. AD7933/AD7934 Ideal Transfer Characteristic
REF
REF
/
can be connected to an external reference source.
V
V
AGND
DGND
V
V
Figure 18. Typical Connection Diagram
DD
IN
IN
REFIN
0.1µF
0
3
–V
REF
/V
1 LSB = 2 × V
1 LSB = 2 × V
AD7933/AD7934
DD
+
REFOUT
+ 1 LSB
0.1µF EXTERNAL V
0.47µF INTERNAL V
REFIN
+
pin is connected to either a 3 V or 5 V
10µF
/V
+
REFOUT
REF
REF
DB11/DB9
V
CONVST
REF
REF
3V/5V
SUPPLY
/4096 (AD7934)
/1024 (AD7933)
V
CLKIN
BUSY
DRIVE
DRIVE
DB0
(RANGE bit = 1). The
W/B
pin is decoupled to AGND
WR
CS
RD
REF
REF
input controls the
0.1µF
+V
REF
+
REF
– 1 LSB
+
Range
10µF
SUPPLY
3V
REF
Rev. B | Page 18 of 32
ANALOG INPUT STRUCTURE
Figure 19 shows the equivalent circuit of the analog input
structure of the AD7933/AD7934 in differential/pseudo
differential modes. In single-ended mode, V
tied to AGND. The four diodes provide ESD protection for the
analog inputs. Ensure that the analog input signals never exceed
the supply rails by more than 300 mV; doing so causes these
diodes to become forward-biased and start conducting into the
substrate. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.
The C1 capacitors in Figure 19 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the sampling capacitors of the ADC and
typically have a capacitance of 45 pF.
For ac applications, removing high frequency components from
the analog input signal is recommended by using an RC low-
pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
drive the analog input from a low impedance source. Large
source impedances significantly affect the ac performance of the
ADC. This may necessitate the use of an input buffer amplifier.
The choice of the op amp is a function of the particular
application.
When no amplifier is used to drive the analog input, limit the
source impedance to low values. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD increases as the source impedance increases
and performance degrades. Figure 20 and Figure 21 show a
graph of the THD vs. source impedance with a 50 kHz input
tone for both V
differential mode, respectively.
Conversion Phase: Switches Open, Track Phase: Switches Closed
V
V
Figure 19. Equivalent Analog Input Circuit,
IN+
IN–
DD
= 5 V and 3 V in single-ended mode and fully
C1
C1
V
V
DD
DD
D
D
D
D
R1
R1
IN−
C2
C2
is internally