AD7934 Analog Devices, AD7934 Datasheet - Page 16
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AD7934
Manufacturer Part Number
AD7934
Description
4-Channel, 1.5 MSPS, 12-Bit Parallel ADC with a Sequencer
Manufacturer
Analog Devices
Datasheet
1.AD7933.pdf
(32 pages)
Specifications of AD7934
Resolution (bits)
12bit
# Chan
4
Sample Rate
1.5MSPS
Interface
Byte,Par
Analog Input Type
Diff-Uni,SE-Uni
Ain Range
(2Vref) p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
Adc Architecture
SAR
Pkg Type
SOP
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AD7933/AD7934
SEQUENCER OPERATION
The configuration of the SEQ0 and SEQ1 bits in the control
register allows use of the sequencer function. Table 11 outlines
the two sequencer modes of operation.
Writing to the Control Register to Program the Sequencer
The AD7933 and AD7934 need 13 full CLKIN periods to
perform a conversion. If the ADC does not receive the full 13
CLKIN periods, the conversion aborts. If a conversion is
Table 10. Analog Input Type Selection
Channel Address
ADD1
0
0
1
1
Table 11. Sequence Selection Modes
SEQ0
0
0
1
1
SEQ1
0
1
0
1
ADD0
0
1
0
1
Sequence Type
Select this configuration when the sequence function is not used. The analog input channel selected on each individual
conversion is determined by the contents of ADD1 and ADD0, the channel address bits, in each prior write operation. This
mode of operation reflects the normal operation of a multichannel ADC, without using the sequencer function, where
each write to the AD7933/AD7934 selects the next channel for conversion.
Not used.
Not used.
Use this configuration in conjunction with ADD1 and ADD0, the channel address bits, to program continuous conversions
on a consecutive sequence of channels. The sequence of channels extends from Channel 0 through to a selected final
channel as determined by the channel address bits in the control register. When in differential or pseudo differential mode,
inverse channels (for example, V
MODE0 = 0, MODE1 = 0
Four Single-Ended
Input Channels
V
V
V
V
V
IN
IN
IN
IN
IN+
0
1
2
3
V
AGND
AGND
AGND
AGND
IN−
IN
1, V
MODE0 = 0, MODE1 = 1
Two Fully Differential
Input Channels
V
V
V
V
V
IN
IN
IN
IN
IN+
IN
0
1
2
3
0) are not converted.
Rev. B | Page 16 of 32
V
V
V
V
V
IN
IN
IN
IN
IN−
1
0
3
2
aborted after applying 12.5 CLKIN periods to the ADC, ensure
that a rising edge of CONVST or a falling edge of CLKIN is
applied to the part before writing to the control register to
program the sequencer. If these conditions are not met, the
sequencer will not be in the correct state to handle being
reprogrammed for another sequence of conversions and the
performance of the converter is not guaranteed.
MODE0 = 1, MODE1 = 0
Two Pseudo Differential
Input Channels
V
V
V
V
V
IN
IN
IN
IN
IN+
0
1
2
3
V
V
V
V
V
IN
IN
IN
IN
IN−
1
0
3
2
MODE0 = 1, MODE1 = 1
Not Used