AD7992 Analog Devices, AD7992 Datasheet - Page 25

• Manufacturer Part Number: AD7992
• Description: 2-Channel, 12-Bit ADC with I2C Compatible Interface in 10-Lead MSOP
• Manufacturer: Analog Devices

Specifications of AD7992

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 79kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOP

MODES OF OPERATION
When supplies are first applied to the AD7992, the ADC
powers up in sleep mode and normally remains in this
shutdown state while not converting. There are three different
methods of initiating a conversion on the AD7992.
MODE 1—USING THE CONVST PIN
A conversion can be initiated on the AD7992 by pulsing the
CONVST signal. The conversion clock for the part is internally
generated so no external clock is required, except when reading
from or writing to the I
CONVST , the AD7992 begins to power up (see point A in
Figure 31). The power-up time from shutdown mode for the
AD7992 is approximately 1 µs; the CONVST signal must
remain high for 1 µs for the part to power up fully. CONVST
can be brought low after this time. The falling edge of the
CONVST signal places the track-and-hold into hold mode; a
conversion is also initiated at this point (point B in Figure 31).
When the conversion is complete, approximately 2 µs later, the
part returns to shutdown (point C in Figure 31) and remains
there until the next rising edge of CONVST . The master can
then read the ADC to obtain the conversion result. The address
pointer register must be pointing to the conversion result
register in order to read back the conversion result.
CONVST
SCA
SDA
A
t
POWER-UP
2
C serial port. On the rising edge of
B
t
CONVERT
C
S
1
7-BIT ADDRESS
Figure 31. Mode 1 Operation
R
A
Rev. 0 | Page 25 of 28
9
1
FIRST DATA BYTE (MSBs)
If the CONVST pulse does not remain high for more than 1 µs,
the falling edge of CONVST still initiates a conversion, but the
result is invalid because the AD7992 is not fully powered up
when the conversion takes place. To maintain the performance
of the AD7992 in this mode, it is recommended that the I
is quiet when a conversion is taking place.
The cycle timer register and Command Bits C4 to C1 in the
address pointer register should contain all 0s when operating
the AD7992 in this Mode 1. The CONVST pin should be tied
low for all other modes of operation. Prior to initiating a
conversion in this mode, a write to the configuration register is
needed to select the channel for conversion. To select both input
channels for conversion, set D5 and D4 in the configuration
register to 1. The ADC services each channel in the sequence
with each CONVST pulse.
Once the conversion is complete, the master can address the
AD7992 to read the conversion result. If further conversions are
required, the SCL line can be taken high while the CONVST
signal is pulsed; then an additional 18 SCL pulses are required
to read the next conversion result.
A
9
SECOND DATA BYTE (LSBs)
A
9
P
AD7992
2
C bus