AD9248 Analog Devices, AD9248 Datasheet
AD9248
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AD9248 Summary of contents
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... Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes GENERAL DESCRIPTION The AD9248 is a dual 14-bit, 20 MSPS/40 MSPS/65 MSPS analog-to-digital converter (ADC). It features dual high performance sample-and hold amplifiers (SHAs) and an integrated voltage reference. The AD9248 uses a multistage differential pipelined architecture with output error correction ...
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... Clock Input and Considerations .............................................. 18 Power Dissipation and Standby Mode ..................................... 19 Digital Outputs ........................................................................... 19 Timing .......................................................................................... 19 Data Format ................................................................................ 20 Voltage Reference ....................................................................... 20 AD9248 LQFP Evaluation Board ................................................. 22 REVISION HISTORY 11/10—Rev Rev. B Changes to Absolute Maximum Ratings Section ......................... 8 Changes to Figure 3 .......................................................................... 9 Add Figure 4; Renumbered Sequentially ....................................... 9 Changes to Theory of Operation Section and Analog Input Section ...
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... 2.7 3.0 3.6 2.7 IV 2.25 3.0 3.6 2. ±0.01 V 180 VI 190 217 V 2.0 Rev Page AD9248 AD9248BST/BCP-65 Typ Max Min Typ Max 14 14 ±0.2 ±1.3 ±0.2 ±1.3 ±0.3 ±2.4 ±0.5 ±2.5 ±0.65 ±0.7 ±0.6 ±1.0 ±0.65 ±1.0 ±2.7 ±2.8 ±2.3 ±4.5 ±2.4 ±4.5 ±2 ± ...
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... Test AD9248BST/BCP-20 AD9248BST/BCP-40 Level Min Typ Max Min I ±0.19 ±1.56 I ±0.19 ±1.56 I ±0.07 ±1.43 I ±0.01 ±0.06 Rev Page AD9248BST/BCP-65 Typ Max Min Typ Max ±0.19 ±1.56 ±0.25 ±1.74 ±0.19 ±1.56 ±0.25 ±1.74 ±0.07 ±1.43 ±0.07 ±1.47 ±0.01 ±0.06 ±0.01 ±0.10 29 for the equivalent analog input structure ...
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... V 25°C I Rev Page AD9248BST/BCP-40 AD9248BST/BCP-65 Min Typ Max Min Typ 73.1 72.8 72.8 73.4 72.3 73.1 72.7 72.3 72.9 71.5 71.2 71.6 69.5 69.0 72.8 72.5 72.0 73.0 71.7 72.7 72.1 71.0 72.3 70.9 70.0 71.0 69.0 68.5 11.8 11.8 11.7 11.8 11.6 11.8 11.7 11.5 11.7 11.5 11.3 11.5 11.2 11.2 85.0 84.0 77.5 86.0 77.5 86.0 83.0 76.0 84.0 80.0 73.0 80.5 AD9248 Max Unit Bits Bits Bits Bits Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc ...
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... Rev Page AD9248BST/BCP-40 AD9248BST/BCP-65 Min Typ Max Min Typ 88.0 85.5 83.5 89.0 81.0 86.0 88.0 82.6 88.5 85.5 79.8 86.0 81.0 75.0 85.0 84.0 77.5 86.0 77.5 86.0 83.0 76.0 84.0 80.0 73.0 80.5 −85.0 −85.0 AD9248BST-40 AD9248BST-65 Typ Max Min Typ 2.0 0.8 +10 −10 +10 − DRVDD − 0.05 0.05 Max Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... Full OUT-OF-RANGE RECOVERY TIME Full 1 The AD9248-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24). 2 Output delay is measured from clock 50% transition to data 50% transition, with load on each output. 3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB. ...
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... AD9248 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Table 5. Parameter ...
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... VREF 8 64-LEAD LFCSP 9 TOP VIEW 10 (Not to Scale) 11 AVDD 12 AGND AGND 16 NOTES 1. THERE IS AN EXPOSED PAD THAT MUST CONNECT TO AGND. Figure 4. 64-Lead LFCSP Pin Configuration Rev Page AD9248 48 D6_A 47 D5_A 46 D4_A 45 D3_A 44 D2_A 43 D1_A D0_A (LSB) 42 DRVDD 41 DRGND 40 39 OTR_B ...
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... AD9248 Table 6. 64-Lead LQFP and 64-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description 1, 4, 13, 16 AGND Analog Ground. 2 VIN+_A Analog Input Pin (+) for Channel A. 3 VIN−_A Analog Input Pin (−) for Channel A. 5, 12, 17, 64 AVDD Analog Power Supply. 6 REFT_A Differential Reference (+) for Channel A. ...
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... Coupling onto one channel being driven by a (−0.5 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Measurement includes all spurs resulting from both direct coupling and mixing components. Rev Page AD9248 /2), this is often referred to as /2) on the output of the ADC. CLOCK ...
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... SFDR = 80.1dBc MHz Figure 9. AD9248-40 Single-Tone SFDR/SNR vs. FS with MHz IN SNR = 68.1dB SINAD = 68.0dB H2 = –83.4dBc H3 = –83.1dBc SFDR = 75.1dBc 25 30 Figure 10. AD9248-20 Single-Tone SFDR/SNR vs. FS with f = 120 MHz IN = 126 MHz IN Rev Page 100 95 90 SFDR SNR 70 ...
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... INPUT FREQUENCY (MHz) Figure 14. AD9248-65 Single-Tone SFDR/SNR vs. f SNR SFDR SNR 100 120 INPUT FREQUENCY (MHz) Figure 15. AD9248-40 Single-Tone SFDR/SNR vs. f SNR SFDR SNR 100 120 INPUT FREQUENCY (MHz) Figure 16. AD9248-20 Single-Tone SFDR/SNR vs. f AD9248 140 ...
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... AD9248 0 –20 –40 –60 IMD = –85dBc –80 –100 –120 FREQUENCY (MHz) Figure 17. Dual-Tone FFT with MHz and –20 –40 IMD = –83dBc –60 –80 –100 –120 FREQUENCY (MHz) Figure 18. Dual-Tone FFT with MHz and – ...
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... SAMPLE RATE (MSPS) Figure 26. Analog Power Consumption vs. FS 2000 4000 6000 8000 10000 12000 14000 16000 CODE Figure 27. AD9248-65 Typical INL 2000 4000 6000 8000 10000 12000 14000 16000 CODE Figure 28. AD9248-65 Typical DNL AD9248 ...
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... AD9248 EQUIVALENT CIRCUITS AVDD VIN+_A, VIN–_A, VIN+_B, VIN–_B Figure 29. Equivalent Analog Input Circuit DRVDD Figure 30. Equivalent Digital Output Circuit AVDD CLK_A, CLK_B DCS, DFS, MUX_SELECT, SHARED_REF Figure 31. Equivalent Digital Input Circuit Rev Page ...
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... The internal voltage reference can be pin-strapped to fixed values adjusted within the same range as discussed in the Internal Reference Connection section. Maximum SNR performance is achieved with the AD9248 set to the largest input span p-p. The relative SNR degradation when changing from 2 V p-p mode p-p mode. ...
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... Under-sampling applications are particularly sensitive to jitter. For optimal performance, especially in cases where aperture jitter may affect the dynamic range of the AD9248 important to minimize input clock jitter. The clock input circuitry should use stable references; for example, use analog power and ground planes to generate the valid high and low digital levels for the AD9248 clock input ...
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... Data outputs are available one propa- gation delay (t to Figure 2 for a detailed timing diagram. The internal duty cycle stabilizer can be enabled on the AD9248 using the DCS pin. This provides a stable 50% duty cycle to internal circuits. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9248. These transients can detract from the converter’ ...
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... REFT_B, and REFB_A must be shorted to REFB_B.) Internal Reference Connection A comparator within the AD9248 detects the potential at the SENSE pin and configures the reference into four possible states, which are summarized in Table 7. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 35), setting VREF ...
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... REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum the internal reference of the AD9248 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 38 depicts how the internal reference voltage is affected by loading ...
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... MUX_SELECT pin. Refer to Table 8 for normal operating jumper positions. OUTPUTS The outputs of the AD9248 (and the data clock discussed earlier) are buffered by 74VHC541s (U2, U3, U7, U10) to ensure the correct load on the outputs of the DUT, as well as the extra drive capability to the next part of the system. The 74VHC541s are latches, but on this evaluation board, they are wired and function as buffers ...
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... EVALUATION BOARD BAND-PASS CIRCUITRY FILTERS Figure 39. PCB Test Setup Rev Page AD9248 JP2 JP3 JP4 JP5 In Out Out Out Out In Out Out Out Out Out In SINE SOURCE LOW JITTER (HP8644) CLOCK CIRCUITRY OUTPUT INPUT AD9248 BUFFERS REFERENCE MODE SELECTION/EXTERNAL REFERENCE/CONTROL LOGIC ...
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... RV3299W 10 kΩ 0805 500 Ω 1206 10 kΩ 0805 22 Ω 1206 0 Ω RCA74204 22 Ω SMA200UP DIP06RCUP T1-1T TBLK06REM LOOPTP RED LOOPTP BLK LOOPMINI WHT LOOPMINI RED 64LQFP7X7 AD9248 SOL20 74VHC541 SOIC-8 AD822 SO8NC7 AD8138 TSSOP-14 74VHC04 ...
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... LQFP EVALUATION BOARD SCHEMATICS Figure 40. Evaluation Board Schematic Rev Page AD9248 ...
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... AD9248 Figure 41. Evaluation Board Schematic (Continued) Rev Page ...
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... Figure 42. Evaluation Board Schematic (Continued) Rev Page AD9248 ...
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... AD9248 C75 C3 C10 10μF 0.1μF 0.1μF 6.3V DATACLKA 1 RP9 22Ω RP9 22Ω 7 OTRA 3 RP9 22Ω 6 DA13 4 RP9 22Ω 5 DA12 1 RP10 22Ω 8 DA11 2 RP10 22Ω 7 DA10 3 RP10 22Ω 6 DA9 4 RP10 22Ω 5 DA8 RP11 22Ω DA7 2 RP11 22Ω 7 DA6 3 RP11 22Ω 6 DA5 ...
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... LQFP PCB LAYERS Figure 44. PCB Top Layer Rev Page AD9248 ...
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... AD9248 Figure 45. Bottom Layer Rev Page ...
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... Figure 46. PCB Ground Plane Rev Page AD9248 ...
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... AD9248 Figure 47. PCB Split Power Plane Rev Page ...
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... Figure 48. PCB Top Silkscreen (Note that the PCB Supports Both the AD9238 and AD9248 LQFP) Rev Page AD9248 ...
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... AD9248 Figure 49. PCB Bottom Silkscreen Rev Page ...
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... E41 to E25 and E30 to E2. R56 and R45 allow for programmable reference mode selection. DATA OUTPUTS The ADC outputs are latched on the PCB at U2, U4. The ADC outputs have the recommended series resistors in line to limit switching transient effects on ADC performance. Rev Page AD9248 ...
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... Capacitors SMBs Power Connector Posts Detachable Connectors Connectors Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistor Resistor Pack Transformers AD9248 SN74LVTH162374 SN74LVC1G04 SN74VCX86 AD8139 Resistors Rev Page Package Value 0201 20 pF 0805 10 μF 0402 0.1 μF TAJD 10 μF 0201 0.1 μ ...
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... PDWN_A 60 MUX_SEL 61 SH_REF 62 CLK_A 63 VD AVDD5 64 EPAD 65 Figure 50. PCB Schematic ( Rev Page D7_B 32 D7B D6_B D6B 31 D5_B 30 D5B DRVDD 29 DRGND 28 D4B D4_B 27 D3B D3_B 26 D2B D2_B 25 D1B D1_B 24 D0B D0_B 23 OEB_B 22 PDWN_B 21 DFS 20 DCS 19 ENCB CLK_B 18 AVDD3 17 VD AD9248 ...
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... AD9248 Figure 51. PCB Schematic ( Rev Page ...
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... Figure 52. PCB Schematic ( Rev Page AD9248 ...
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... AD9248 LFCSP PCB LAYERS Figure 53. PCB Top-Side Silkscreen Rev Page ...
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... Figure 54. PCB Top-Side Copper Routing Rev Page AD9248 ...
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... AD9248 Figure 55. PCB Ground Layer Rev Page ...
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... Figure 56. PCB Split Power Plane Rev Page AD9248 ...
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... AD9248 Figure 57. PCB Bottom-Side Copper Routing Rev Page ...
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... THERMAL CONSIDERATIONS The AD9248 LFCSP has an integrated heat slug that improves the thermal and electrical properties of the package when locally attached to a ground plane at the PCB. A thermal (filled) via array to a ground plane beneath the part provides a path for heat to escape the package, lowering junction temperature ...
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... AD9248 OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW BSC SQ PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE 0.75 1.60 0.60 MAX 0. PIN 1 0.20 0.09 7° 3.5° 16 0° 17 0.08 COPLANARITY VIEW A 0.40 BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BBD Figure 60. 64-Lead Low Profile Quad Flat Package [LQFP] ...
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... Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board with AD9248BSTZ-65 Evaluation Board with AD9248BCPZ-65 Rev Page AD9248 Package Option ST-64-1 ...
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... AD9248 NOTES ©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04446–0–11/10(B) Rev Page ...