AD7938-6 Analog Devices, AD7938-6 Datasheet - Page 16

• Manufacturer Part Number: AD7938-6
• Description: 8-Channel, 625 kSPS, 12-Bit Parallel ADCs with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7938-6

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 625kSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7938-6
CIRCUIT INFORMATION
The AD7938-6 is a fast, 8-channel, 12-bit, single-supply,
successive approximation analog-to-digital converter. The part
can operate from a 2.7 V to 5.25 V power supply and features
throughput rates up to 625 kSPS.
The AD7938-6 provides the user with an on-chip track-and-hold,
an accurate internal reference, an analog-to-digital converter, and
a parallel interface housed in a 32-lead LFCSP or TQFP package.
The AD7938-6 has eight analog input channels that can be
configured to be eight single-ended inputs, four fully differential
pairs, four pseudo differential pairs, or seven pseudo differential
inputs with respect to one common input. There is an on-chip
user-programmable channel sequencer that allows the user to select
a sequence of channels through which the ADC can progress and
cycle with each consecutive falling edge of CONVST .
The analog input range for the AD7938-6 is 0 V to V
2 × V
register. The output coding of the ADC can be either straight
binary or twos complement, depending on the status of the
CODING bit in the control register.
The AD7938-6 provides flexible power management options to
allow the user to achieve the best power performance for a given
throughput rate. These options are selected by programming the
power management bits, PM1 and PM0, in the control register.
CONVERTER OPERATION
The AD7938-6 is a successive approximation ADC based
around two capacitive digital-to-analog converters. Figure 14
and Figure 15 show simplified schematics of the ADC in
acquisition and conversion phase, respectively. The ADC
comprises control logic, an SAR, and two capacitive digital-to-
analog converters. Both figures show the operation of the ADC
in differential/pseudo differential mode. Single-ended mode
operation is similar but V
acquisition phase, SW3 is closed, SW1 and SW2 are in Position
A, the comparator is held in a balanced condition and the
sampling capacitor arrays acquire the differential signal on the
input.
V
V
IN+
IN–
REF
depending on the status of the RANGE bit in the control
B
A
A
B
V
REF
SW1
SW2
Figure 14. ADC Acquisition Phase
C
C
S
S
IN−
is internally tied to AGND. In
SW3
COMPARATOR
CAPACITIVE
CAPACITIVE
CONTROL
LOGIC
REF
DAC
DAC
or 0 V to
Rev. C | Page 16 of 32
When the ADC starts a conversion (see Figure 15), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge
redistribution DACs are used to add and subtract fixed amounts
of charge from the sampling capacitor arrays to bring the
comparator back into a balanced condition. When the comparator
is rebalanced, the conversion is complete. The control logic
generates the output code of the ADC. The output impedances
of the sources driving the V
otherwise, the two inputs have different settling times, resulting
in errors.
ADC TRANSFER FUNCTION
The output coding for the AD7938-6 is either straight binary or
twos complement, depending on the status of the CODING bit
in the control register. The designed code transitions occur at
successive LSB values (that is, 1 LSB, 2 LSBs, and so on) and the
LSB size is V
AD7938-6 for both straight binary and twos complement
output coding are shown in Figure 16 and Figure 17,
respectively.
V
V
IN+
IN–
000...010
000...001
000...000
111...110
111...000
011...111
111...111
B
A
A
B
Figure 16. AD7938-6 Ideal Transfer Characteristic
REF
0V
V
NOTE: V
REF
/4096. The ideal transfer characteristics of the
SW1
SW2
with Straight Binary Output Coding
Figure 15. ADC Conversion Phase
1 LSB
C
C
S
S
REF
IS EITHER V
ANALOG INPUT
IN+
SW3
and the V
1 LSB = V
REF
COMPARATOR
OR 2 × V
REF
IN−
/4096
REF
pins must match;
+V
REF
Data Sheet
CAPACITIVE
CAPACITIVE
– 1 LSB
CONTROL
LOGIC
DAC
DAC