AD7993 Analog Devices, AD7993 Datasheet - Page 29

• Manufacturer Part Number: AD7993
• Description: 4-Channel, 10-Bit ADC with I2C Compatible Interface in 16-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7993

• Resolution (bits): 10bit
• # Chan: 4
• Sample Rate: 188kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: SOP

MODE 2—COMMAND MODE
This mode allows a conversion to be automatically initiated any
time a write operation occurs. In order to use this mode,
Command Bits C4 to C1 in the address pointer byte, shown in
Table 7, must be programmed.
To select a single analog input for conversion in this mode,
the user must set bits C4 to C1of the address pointer byte to
indicate which channel to convert (see Table 27). When all four
command bits are 0, this mode is not in use.
A sequence can also be set up for this mode. If more than one
command bit is set in the address pointer byte, the ADC starts
converting on the lowest channel in the sequence and then the
next lowest until all the channels in the sequence have been
converted. The ADC stops converting the sequence when it
receives a STOP bit.
Figure 29 illustrates a 2-byte read operation from the conver-
sion result register. This operation is normally preceded by a
write to the address pointer register so that the following read
accesses the desired register, in this case the conversion result
register (Figure 26). If Command Bits C4 to C1 are set when the
contents of the address pointer register are being loaded, the
AD7993/AD7994 begin to power up and convert the selected
channel(s). Power-up begins on the fifth SCL falling edge of the
address point byte (see Point A in Figure 33).
Table 27. Address Pointer Byte
C4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
P3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P1
P0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Not selected
V
V
Sequence between V
V
Sequence between V
Sequence between V
Sequence between V
V
Sequence between V
Sequence between V
Sequence between V
Sequence between V
Sequence between V
Sequence between V
Sequence between V
Mode 2, Convert On
IN
IN
IN
IN
1
2
3
4
Rev. 0 | Page 29 of 32
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
1 and V
1 and V
2 and V
1, V
1 and V
2 and V
1, V
3 and V
1, V
2, V
1, V
IN
IN
IN
IN
IN
2, and V
2, and V
3, and V
3, and V
2, V
Table 27 shows the channel selection in this mode via
Command Bits C4 to C1 in the address pointer register. The
wake-up and conversion times combined should take
approximately 3 µs. Following this, the AD7993/AD7994 must
be addressed again to indicate that a read operation is required.
The read then takes place from the conversion result register.
This read accesses the conversion result from the channel
selected via the command bits. If the Command Bits C2 and C1
were set to 1, 1, then a four byte read would be necessary. The
first read accesses the data from the conversion on V
this read takes place, a conversion occurs on V
read accesses this data from V
mode operates.
When operating the AD7994-1/AD7993-1 in Mode 2 with a
high speed mode, 3.4 MHz SCL, the conversion may not be
complete before the master tries to read the conversion result.
If this is the case, the AD7994-1/AD7993-1 hold the SCL line
low during the ACK clock after the read address until the con-
version is complete. When the conversion is complete, the
AD7994-1/AD7993-1 release the SCL line and the master can
then read the conversion result.
After the conversion is initiated by setting the command bits in
the address pointer byte, if the AD7993/AD7994 receive a stop
or NACK from the master, the devices stop converting.
IN
IN
IN
IN
IN
IN
IN
2
3
3
4
4
4
3, and V
IN
IN
IN
IN
3
4
4
4
IN
4
Comments
With the pointer bits set to all 0s, the next
read accesses the results of the conversion
result register.
IN
2. Figure 34 illustrates how this
AD7993/AD7994
IN
2. The second
IN
1. While