AD7997 Analog Devices, AD7997 Datasheet - Page 15

• Manufacturer Part Number: AD7997
• Description: 8-Channel, 10-Bit ADC with I2C Compatible Interface in 20-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7997

• Resolution (bits): 10bit
• # Chan: 8
• Sample Rate: 79kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: SOP

CIRCUIT INFORMATION
The AD7997/AD7998 are low power, 10- and 12-bit, single-
supply, 8-channel A/D converters. The parts can be operated
from a 2.7 V to 5.5 V supply.
The AD7997/AD7998 have an 8-channel multiplexer, an on-
chip track-and-hold, an A/D converter, an on-chip oscillator,
internal data registers, and an I
housed in a 20-lead TSSOP. This package offers considerable
space-saving advantages over alternative solutions. The
AD7997/AD7998 require an external reference in the range of
1.2 V to V
The AD7997/AD7998 typically remain in a power-down state
while not converting. When supplies are first applied, the parts
come up in a power-down state. Power-up is initiated prior to
a conversion, and the device returns to shutdown when the
conversion is complete. Conversions can be initiated on the
AD7997/AD7998 by pulsing the CONVST signal, using an
automatic cycle interval mode, or a command mode where
wake-up and a conversion occur during a write address
function (see the Modes of Operation section). When the
conversion is complete, the AD7997/AD7998 again enter
shutdown mode. This automatic shutdown feature allows power
saving between conversions. This means any read or write
operation across the I
in shutdown.
CONVERTER OPERATION
The AD7997/AD7998 are successive approximation analog-to-
digital converters based around a capacitive DAC. Figure 18
and Figure 19 show simplified schematics of the ADC during
the acquisition and conversion phase, respectively. Figure 18
shows the acquisition phase. SW2 is closed and SW1 is in
position A, the comparator is held in a balanced condition,
and the sampling capacitor acquires the signal on V
AGND
V
IN
DD
A
.
SW1
B
Figure 18. ADC Acquisition Phase
2
C interface can occur while the device is
SW2
2
C-compatible serial interface, all
COMPARATOR
CAPACITIVE
IN
CONTROL
.
LOGIC
DAC
Rev. 0 | Page 15 of 32
At the beginning of a conversion, SW2 opens and SW1 moves
to position B, causing the comparator to become unbalanced, as
shown in Figure 19. The input is disconnected once the con-
version begins. The control logic and the capacitive DAC are
used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 20 shows the ADC transfer characteristic.
ADC Transfer Function
The output coding of the AD7997/AD7998 is straight binary.
The designed code transitions occur at successive integer LSB
values (1 LSB, 2 LSB, and so on). The LSB size is REF
the AD7997 and REF
the ideal transfer characteristic for the AD7997/AD7998.
AGND
V
IN
111...111
111...110
111...000
011...111
000...010
000...001
000...000
SW1
A
Figure 20. AD7997/AD7998 Transfer Characteristic
B
Figure 19. ADC Conversion Phase
AGND + 1LSB
IN
/4096 for the AD7998. Figure 20 shows
SW2
ANALOG INPUT
0V TO REF
AD7997 1LSB = REF
AD7998 1LSB = REF
IN
COMPARATOR
+REF
AD7997/AD7998
IN
– 1LSB
IN
IN
CAPACITIVE
/1024
/4096
CONTROL
LOGIC
DAC
IN
/1024 for