AD7451 Analog Devices, AD7451 Datasheet - Page 17

• Manufacturer Part Number: AD7451
• Description: Pseudo Differential Input, 1 MSPS, 12-Bit ADC in an 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7451

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

Timing Example 1
Having f
cycle time of
A cycle consists of
Therefore, if t
This 296 ns satisfies the requirement of 290 ns for t
From Figure 28, t
where t
satisfying the minimum requirement of 60 ns.
1/Throughput = 1/1,000,000 = 1 μs
t
10 ns + 12.5 (1/18 MHz) + t
t
2.5 (1/f
2
ACQUISITION
+ 12.5 (1/f
8
SCLK
= 35 ns. This allows a value of 122 ns for t
SCLK
= 18 MHz and a throughput rate of 1 MSPS gives a
2
= 10 ns, then
= 296 ns
) + t
SCLK
SCLK
ACQUISITION
CS
8
) + t
= t
t
QUIET
10ns
2
ACQUISITION
comprises
1
ACQUISITION
= 1 μs
2
= 1 μs
3
QUIET
12.5(1/
ACQUISITION
Figure 28. Serial Interface Timing Example
4
,
f
SCLK
t
5
)
Rev. D | Page 17 of 24
.
5
t
CONVERT
1/THROUGHPUT
Timing Example 2
Having f
cycle time of
A cycle consists of
Therefore, if t
This 664 ns satisfies the requirement of 290 ns for t
From Figure 28, t
where t
satisfying the minimum requirement of 60 ns.
As in this example and with other slower clock values, the signal
can already be acquired before the conversion is complete, but it
is still necessary to leave 60 ns minimum t
sions. In Example 2, the signal is fully acquired at approximately
Point C in Figure 28.
13
B
1/Throughput = 1/315,000 = 3.174 μs
t
10 ns + 12.5 (1/5 MHz) + t
t
2.5 (1/f
2
ACQUISITION
+ 12.5 (1/f
8
SCLK
= 35 ns. This allows a value of 129 ns for t
14
t
SCLK
6
= 5 MHz and a throughput rate of 315 kSPS gives a
2
is 10 ns, then
= 664 ns
) + t
SCLK
ACQUISITION
C
15
8
t
) + t
ACQUISITION
= t
t
8
QUIET
ACQUISITION
16
comprises
ACQUISITION
t
QUIET
= 3.174 μs
AD7441/AD7451
= 3.174 μs
QUIET
between conver-
QUIET
ACQUISITION
,
.