AD7652 Analog Devices, AD7652 Datasheet - Page 22

no-image

AD7652

Manufacturer Part Number
AD7652
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD7652

Resolution (bits)
16bit
# Chan
1
Sample Rate
500kSPS
Interface
Par,Ser,SPI
Analog Input Type
Diff-Uni
Ain Range
Uni (Vref),Uni 2.5V
Adc Architecture
SAR
Pkg Type
CSP,QFP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7652AST
Manufacturer:
ADI
Quantity:
273
Part Number:
AD7652ASTZ
Manufacturer:
ADI
Quantity:
273
Part Number:
AD7652ASTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD7652ASTZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7652ASTZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
AD7652
SLAVE SERIAL INTERFACE
External Clock
The AD7652 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/ INT pin is held
HIGH. In this mode, several methods can be used to read the
data. The external serial clock is gated by CS . When CS and RD
are both LOW, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally HIGH or normally LOW when
inactive. F
diagrams of these methods.
igure 34
and F
SDOUT
CNVST
SDOUT
BUSY
SCLK
BUSY
SCLK
SDIN
CS
igure 35
RD
t
16
Figure 35. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
t
t
show the detailed timing
t
31
16
3
t
t
31
33
X
Figure 34. Slave Serial Data Timing for Reading (Read after Convert)
X
t
36
t
1
36
1
t
35
t
D15
35
t
37
D15
X15
t
37
t
34
2
2
EXT/INT = 1
D14
t
D14
X14
EXT/INT = 1
32
t
32
3
Rev. 0 | Page 22 of 28
3
D13
X13
D13
INVSCLK = 0
While the AD7652 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins or
degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7652 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that is toggling only when BUSY is
LOW, or, more importantly, that it does not transition during the
latter half of BUSY HIGH.
INVSCLK = 0
14
14
15
15
D1
X1
D1
RD = 0
16
16
RD = 0
D0
X0
D0
17
X15
Y15
18
02964-0-017
02965-0-018
X14
Y14

Related parts for AD7652