AD9865 Analog Devices, AD9865 Datasheet - Page 6

• Manufacturer Part Number: AD9865
• Description: 10-Bit Broadband Modem Mixed Signal Front End (MxFE®)
• Manufacturer: Analog Devices

Specifications of AD9865

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 6.3 V p-p,8 mV p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9865
Parameter
POWER CONSUMPTION (Half-Duplex Operation with f
POWER CONSUMPTION OF FUNCTIONAL BLOCKS
MAXIMUM ALLOWABLE POWER DISSIPATION
STANDBY POWER CONSUMPTION
POWER DOWN DELAY (USING PWR_DWN PIN)
POWER UP DELAY (USING PWR_DWN PIN)
1
2
DIGITAL SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; R
Table 4.
Parameter
CMOS LOGIC INPUTS
CMOS LOGIC OUTPUTS (C
RESET
Default power-up settings for MODE = HIGH and CONFIG = LOW, IOUTP_FS = 20 mA, does not include IAMP’s current consumption, which is application dependent.
Default power-up settings for MODE = LOW and CONFIG = LOW.
Tx Mode
Rx Mode
RxPGA and LPF
ADC
TxDAC
IAMP (Programmable)
Reference
CLK PLL and Synthesizer
IS_TOTAL (Total Supply Current)
RxPGA and LPF
ADC
TxDAC
IAMP
CLK PLL and synthesizer
RxPGA and LPF
ADC
TxDAC
IAMP
CLK PLL and Synthesizer
High Level Input Voltage
Low Level Input Voltage
Input Leakage Current
Input Capacitance
High Level Output Voltage (I
Low Level Output Voltage (I
Output Rise/Fall Time (High Strength Mode and C
Output Rise/Fall Time (Low Strength Mode and C
Output Rise/Fall Time (High Strength Mode and C
Output Rise/Fall Time (Low Strength Mode and C
Minimum Low Pulse Width (Relative to f
I
I
I
I
AVDD
DVDD
AVDD
DVDD
+ I
+ I
+ I
+ I
CLKVDD
CLKVDD
DRVDD
DRVDD
LOAD
= 5 pF)
OH
OH
= 1 mA)
= 1 mA)
ADC
)
1
(I
LOAD
LOAD
LOAD
LOAD
AVDD
DATA
= 15 pF)
= 5 pF)
= 15 pF)
= 5 pF)
+ I
= 50 MSPS)
CLKVDD
Rev. A | Page 6 of 48
)
2
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
SET
Temp
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
= 2 kΩ, unless otherwise noted.
Test Level
VI
VI
VI
VI
VI
VI
VI
VI
VI
Test Level
IV
IV
IV
IV
III
III
III
III
III
III
IV
III
III
III
III
III
III
III
III
III
III
Min
DRVDD – 0.7
DRVDD – 0.7
1
Min
10
Typ
112
46
225
36.5
87
108
38
170
107
13
440
12
20
20
27
7.8
88
13
20
20
Typ
3
1.5/2.3
1.9/2.7
0.7/0.7
1.0/1.0
Max
130
49.5
253
39
120
1.66
Max
0.4
12
0.4
Unit
V
V
µA
pF
V
V
ns
ns
ns
ns
Clock
cycles
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
W
mA
ns
ns
ns
ns
ns
µs
ns
µs
ns
µs