AD7910 Analog Devices, AD7910 Datasheet - Page 6

• Manufacturer Part Number: AD7910
• Description: 250 kSPS, 10-Bit ADC in 6 Lead SC70
• Manufacturer: Analog Devices

Specifications of AD7910

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SC70,SOP

AD7910/AD7920
TIMING SPECIFICATIONS
V
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
POWER-UP
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Minimum f
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 1.8 V when V
Measured with a 50 pF load capacitor.
t
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
T
See Power-Up Time section.
6, 7
DD
4
5, 6
8
7
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
values apply to t
2
= 2.35 V to 5.25 V, T
8
SCLK
1
at which specifications are guaranteed.
8
minimum values also.
AD7910/AD7920
Limit at T
10
5
14 × t
16 × t
50
10
10
22
40
0.4 × t
0.4 × t
10
9.5
7
36
See Note 7
1
A
SCLK
SCLK
SCLK
SCLK
= T
MIN
MIN
, T
to T
MAX
MAX
, unless otherwise noted.
Figure 2. Load Circuit for Digital Output Timing Specifications
Unit
kHz min
MHz max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
μs max
TO OUTPUT
PIN
3
50pF
Rev. C | Page 6 of 24
C
L
Description
AD7910
AD7920
Minimum quiet time required between bus relinquish and start of next
conversion
Minimum CS pulse width
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
V
3.3 V < V
V
SCLK falling edge to SDATA three-state
SCLK falling edge to SDATA three-state
Power-up time from full power-down
200μA
200μA
DD
DD
≤ 3.3 V
> 3.6 V
DD
≤ 3.6 V
I
I
OL
OH
DD
) and timed from a voltage level of 1.6 V.
1.6V
8
, shown in the Timing Specifications is the true bus relinquish
DD
= 2.35 V and 0.8 V or 2.0 V for V
DD
> 2.35 V.