AD7478A Analog Devices, AD7478A Datasheet - Page 17

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AD7478A

Manufacturer Part Number
AD7478A
Description
8-Bit, 1 MSPS, Low-Power A/D Converter in SC70 and MSOP Packages
Manufacturer
Analog Devices
Datasheet

Specifications of AD7478A

Resolution (bits)
8bit
# Chan
1
Sample Rate
1.2MSPS
Interface
Ser,SPI
Analog Input Type
SE-Uni
Ain Range
Uni Vdd
Adc Architecture
SAR
Pkg Type
SC70,SOP

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Table 8 provides typical performance data with various op amps
used as the input buffer for a 100 kHz input tone at room
temperature under the same setup conditions.
Table 8. AD7476A Typical Performance with Various Input
Buffers, V
Op Amp in the Input Buffer
AD711
AD797
AD845
When no amplifier is used to drive the analog input, limit the
source impedance to low values. The maximum source imped-
ance depends on the amount of total harmonic distortion (THD)
that can be tolerated. The THD increases as the source impedance
increases, degrading the performance (see Figure 13).
DD
= 3 V
AD7476A SNR Performance (dB)
72.3
72.5
71.4
Rev. F | Page 17 of 28
DIGITAL INPUTS
The digital inputs applied to the AD7476A/AD7477A/AD7478A
are not limited by the maximum ratings that limit the analog
input. Instead, the digital inputs applied can reach 7 V and are
not restricted by the V
For example, if operating the AD7476A/AD7477A/AD7478A
with a V
However, note that the data output on SDATA still has 3 V logic
levels when V
being restricted by the V
sequencing issues are avoided. If CS or SCLK are applied before
V
input if a signal greater than 0.3 V were applied prior to V
DD
, there is no risk of latch-up as there would be on the analog
DD
of 3 V, use 5 V logic levels on the digital inputs.
DD
= 3 V. Another advantage of SCLK and CS not
AD7476A/AD7477A/AD7478A
DD
DD
+ 0.3 V limit as on the analog input.
+ 0.3 V limit is that power supply
DD
.

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