AD7484 Analog Devices, AD7484 Datasheet - Page 13

• Manufacturer Part Number: AD7484
• Description: 14-Bit, 3 MSPS SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7484

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 3MSPS
• Interface: Par
• Analog Input Type: SE-Uni
• Ain Range: Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: QFP

For higher input bandwidth applications, the
(also available as a dual
choice to drive the AD7484. Figure 15 shows the analog input
circuit used to obtain the data for the FFT plot shown in Figure 4.
A bipolar analog signal is applied to the terminal and biased
up with a stable, low noise dc voltage connected, as shown in
Figure 12. A 10 pF compensation capacitor is connected between
Pin 5 of the AD8021 and the negative supply. The AD8021 is
supplied with +12 V and −12 V supplies. The supply pins are
decoupled as close to the device as possible, with both a 0.1 µF
and a 10 µF capacitor connected to each pin. In each case, the
0.1 µF capacitor should be the closer of the two caps to the
device. The AD8021 logic reference pin is tied to analog ground,
and the DISABLE
information on the AD8021 is available at www.analog.com.
ADC TRANSFER FUNCTION
The output coding of the AD7484 is straight binary. The designed
code transitions occur midway between the successive integer
LSB values, that is, 1/2 LSB, 3/2 LSB, and so on. The LSB size is
V
shown in Figure 16. This transfer characteristic may be shifted
as detailed in the Offset/Overrange section.
POWER SAVING
The AD7484 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. In addition, the
AD7484 features two power saving modes, nap and standby.
These modes are selected by bringing either the NAP pin or the
STBY pin to a logic high, respectively.
When operating the AD7484 in normal fully powered mode,
the current consumption is 18 mA during conversion and the
quiescent current is 12 mA. Operating at a throughput rate of
1 MSPS, the conversion time of 300 ns contributes 27 mW to
the overall power dissipation.
REF
/16,384. The nominal transfer characteristic for the AD7484 is
(300 ns/1 μs) × (5 V × 18 mA) = 27 mW
111...111
111...110
111...000
011...111
000...010
000...001
000...000
Figure 16. AD7484 Transfer Characteristic
pin is tied to the positive supply. Detailed
0V
0.5LSB
AD8022
ANALOG INPUT
op amp) is the recommended
1LSB = V
+V
REF
REF
/16384
AD8021
– 1.5LSB
op amp
Rev. C | Page 13 of 20
For the remaining 700 ns of the cycle, the AD7484 dissipates
42 mW of power.
Therefore, the power dissipated during each cycle is
Figure 17 shows the AD7484 conversion sequence operating in
normal mode.
In nap mode, almost all of the internal circuitry is powered down.
In this mode, the power dissipation is reduced to 2.5 mW. When
using an external reference, there must be a minimum of 300 ns
from exiting nap mode to initiating a conversion. This is necessary
to allow the internal circuitry to settle after power-up and for
the track-and-hold to properly acquire the analog input signal.
The internal reference cannot be used in conjunction with the
nap mode.
If the AD7484 is put into nap mode after each conversion, the
average power dissipation is reduced, but the throughput rate is
limited by the power-up time. Using the AD7484 with a through-
put rate of 500 kSPS while placing the part in nap mode after
each conversion results in average power dissipation as follows:
The power-up phase contributes
The conversion phase contributes
While in nap mode for the rest of the cycle, the AD7484
dissipates only 1.75 mW of power.
Therefore, the power dissipated during each cycle is
CONVST
(700 ns/1 μs) × (5 V × 12 mA) = 42 mW
27 mW + 42 mW = 69 mW
(300 ns/2 μs) × (5 V × 12 mA) = 9 mW
(300 ns/2 μs) × (5 V × 18 mA) = 13.5 mW
(1400 ns/2 μs) × (5 V × 0.5 mA) = 1.75 mW
9 mW + 13.5 mW + 1.75 mW = 24.25 mW
BUSY
Figure 17. Normal Mode Power Dissipation
300ns
1µs
700ns
AD7484