AD7843 Analog Devices, AD7843 Datasheet - Page 16

• Manufacturer Part Number: AD7843
• Description: Touch Screen Digitizer
• Manufacturer: Analog Devices

Specifications of AD7843

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 125kSPS
• Interface: Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: SOP

AD7843
SERIAL INTERFACE
Figure 24 shows the typical operation of the serial interface of
the AD7843. The serial clock provides the conversion clock and
also controls the transfer of information to and from the
AD7843. One complete conversion can be achieved with 24
DCLK cycles.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS takes the BUSY output and the serial bus
out of three-state. The first eight DCLK cycles are used to write
to the control register via the DIN pin. The control register is
updated in stages as each bit is clocked in. Once the converter
has enough information about the following conversion to set
the input multiplexer and switches appropriately, the converter
enters acquisition mode and, if required, the internal switches
are turned on. During the acquisition mode, the reference input
data is updated. After the three DCLK cycles of acquisition, the
X/Y SWITCHES
(SER/DFR HIGH)
X/Y SWITCHES
(SER/DFR LOW)
NOTES
1
1
2
1
Y DRIVERS ARE ON WHEN X+ IS SELECTED INPUT CHANNEL (A2–A0 = 001); X DRIVERS ARE ON WHEN Y+ IS SELECTED INPUT CHANNEL (A2–A0 = 101).
WHEN PD1, PD0 = 10 OR 00, Y– WILL TURN ON AT THE END OF THE CONVERSION.
DRIVERS WILL REMAIN ON IF POWER-DOWN MODE IS 11 (NO POWER-DOWN) UNTIL SELECTED INPUT CHANNEL, REFERENCE MODE,
OR POWER-DOWN MODE IS CHANGED.
DOUT
DCLK
BUSY
DIN
CS
1,2
1
Figure 24. Conversion Timing, 24 DCLKS per Conversion Cycle, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.
THREE-STATE
THREE-STATE
(START) IDLE
S
1
A2
OFF
OFF
A1
A0
MODE
SER/
DFR
ACQUIRE
t
PD1 PD0
ON
ACQ
8
1
Rev. B | Page 16 of 20
(MSB)
11
10
ON
9
control word is complete (the power management bits are now
updated) and the converter enters conversion mode. At this
point, track-and-hold goes into hold mode, the input signal is
sampled, and the BUSY output goes high (BUSY returns low on
the next falling edge of DCLK). The internal switches may also
turn off at this point if in single-ended mode.
The next 12 DCLK cycles are used to perform the conversion
and to clock out the conversion result. If the conversion is
ratiometric (SER/ DFR set low), the internal switches are on
during the conversion. A 13th DCLK cycle is needed to allow
the DSP/microcontroller to clock in the LSB. Three more DCLK
cycles clock out the three trailing zeroes and complete the 24
DCLK transfer. The 24 DCLK cycles can be provided from a
DSP or via three bursts of 8 clock cycles from a microcontroller.
8
CONVERSION
7
OFF
6
5
8
4
1
3
2
1
(LSB)
0
ZERO FILLED
IDLE
OFF
THREE-STATE
THREE-STATE
8