AD9226 Analog Devices, AD9226 Datasheet
AD9226
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AD9226 Summary of contents
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... MSPS data rates. There are no missing codes over the full operating temperature range (guaranteed). The input of the AD9226 allows for easy interfacing to both imaging and communications systems. With a truly differential input structure, the user can select a variety of input ranges and offsets including single-ended applications ...
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... IDRVDD 4, 5 POWER CONSUMPTION NOTES 1 Includes internal voltage reference error. 2 Excludes internal voltage reference error. 3 Load regulation with 1 mA load current (in addition to that required by the AD9226). 4 AVDD = DRVDD = 3 V Specifications subject to change without notice MSPS, VREF = 2.0 V, Differential inputs, T SAMPLE Temp ...
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... Output Enable Delay NOTES The clock period may be extended to 10 µs without degradation in specified performance @ 25° When MODE pin is tied to AVDD or grounded, the AD9226 SSOP is not affected by clock duty cycle. 3 LQFP package. Specifications subject to change without notice. ANALOG INPUT CLOCK ...
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... AD9226–SPECIFICATIONS AC SPECIFICATIONS (AVDD = 5 V, DRVDD = Parameter SIGNAL-TO-NOISE RATIO f = 2.5 MHz MHz MHz MHz 200 MHz IN SIGNAL-TO-NOISE RATIO AND DISTORTION f = 2.5 MHz MHz MHz MHz 200 MHz IN TOTAL HARMONIC DISTORTION f = 2.5 MHz MHz ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9226 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... CLK 1 28 DRVDD (LSB) BIT 12 2 DRVSS 27 BIT AVDD BIT AVSS BIT VINB BIT VINA AD9226 BIT MODE TOP VIEW (Not to Scale) BIT CAPT BIT CAPB BIT REFCOM (AVSS) BIT 3 11 VREF 18 BIT 2 ...
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... The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal levels are lowered dBFS (always related back to converter full scale). AD9226 ...
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... AD9226 DRVDD AVDD AVSS DRVDD DRVDD DRVSS DRVSS AVDD AVSS AVDD AVSS ...
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... SFDR = 87.6dBc –40 –50 –60 –70 –80 –90 –100 –110 –120 0 6.5 13 19.5 FREQUENCY – MHz Typical Performance Characteristics–AD9226 = Differential Input Span 100 SNR = 69.9dBc SINAD = 69.8dBc 90 ENOB = 11.4BITS THD = –86.4dBc SFDR = 88.7dBc 32.5 – ...
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... AD9226 75 2V SPAN, DIFFERENTIAL SPAN, SINGLE-ENDED FREQUENCY – MHz –45 2V SPAN, SINGLE-ENDED –50 –55 –60 –65 –70 –75 –80 –85 – FREQUENCY – MHz 72 – FREQUENCY – MHz 12 11 SPAN, ...
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... AD9226 f = 2MHz 20MHz SAMPLE RATE – MSPS SFDR – CLOCK STABILIZER ON SINAD – CLOCK STABILIZER OFF POSITIVE DUTY CYCLE 1k 1500 ...
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... AD9226 AD9226–Typical IF Sampling Performance Characteristics (AVDD = 5.0 V, DRVDD = 3 MSPS with CLK Stabilizer Enabled, T SAMPLE V = 2.0 V, unless otherwise noted.) REF 0 SNR = 70.2dBFS –10 SFDR = 89dBFS NOISE FLOOR = 145.33dBFS/Hz –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 FREQUENCY – ...
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... SFDR – 2V SPAN 80 75 SNR/NOISE FLOOR – 2V SPAN 70 65 SNR/NOISE FLOOR – 1V SPAN –24 –21 1000 AD9226 165.1 SFDR – 2V SPAN 160.1 155.1 150.1 SNR/NOISE FLOOR – 2V SPAN 145.1 140.1 135.1 –18 –15 –12 –9 –6 A – dBFS IN 160 ...
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... SENSE REFCOM OVERVIEW OF INPUT AND REFERENCE CONNECTIONS The overall input span of the AD9226 is equal to the potential at the VREF pin. The VREF potential may be obtained from the internal AD9226 reference or an external source (see Reference Operation section). In differential applications, the center point of the span is obtained by the common-mode level of the signals ...
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... F the Nyquist frequency (i.e., f The circuit shown in Figure ideal method of applying 0 differential dc drive to the AD9226. It uses an AD8138 to derive a differential signal from a single-ended one. Figure 6b 0.1 F illustrates its performance. Figure 7 presents the schematic of the suggested transformer circuit. The circuit uses a Minicircuits RF transformer, model T1-1T, which has an impedance ratio of four (turns ratio of 2). The schematic assumes that the signal source has a 50 Ω ...
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... Various high- speed performance amplifiers that are restricted to +5 V/–5 V operation and/or specified for 5 V single-supply operation can be easily configured for the input span of the AD9226. Simple AC Interface Figure 9a shows a typical example of an ac-coupled, single- ended configuration of the SSOP package ...
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... F Figure 11a shows a simplified model of the internal voltage refer- VREF ence of the AD9226. A reference amplifier buffers fixed reference. The output from the reference amplifier, A1, appears on the VREF pin. The voltage on the VREF pin determines 0.1 F the full-scale input span of the ADC ...
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... VREF. Thus the valid input range extends from (VREF + VREF/2) to (VREF – VREF/2). For example, if the REF191, a 2.048 V external reference, is selected, the input span extends to 2.048 V. In this case, 1 LSB of the AD9226 corresponds to 0.5 mV essential that a minimum µF capacitor, in parallel with a 0.1 µF low-inductance ceramic capacitor, decouple the reference output to ground ...
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... connected to AVDD, the output data format will be two’s complement. See Table II. Pin 43 of the LQFP package controls the clock stabilizer function of the AD9226. If the pin is connected to AVSS, both clock edges will be used in the conversion architecture. When Pin 43 is connected to AVDD, the internal duty cycle will be determined by the clock stabilizer function within the ADC ...
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... Bias Decoupling The CML and VR are analog bias points used internally by the AD9226. These pins must be decoupled with at least a 0.1 µF DRVDD = 3V capacitor as shown in Figure 18. The dc level of CML is approxi- mately AVDD/2. This voltage should be buffered used for any external biasing ...
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... CLOCK and AUXCLK. The CLOCK input should be selected if the frequency of the input clock signal is at the target sample rate of the AD9226. The input clock signal is ac-coupled and level-shifted to the switch- ing threshold of a 74VHC02 clock driver. The AUXCLK input should be selected in applications requiring the lowest jitter and SNR performance (i ...
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... C23 RED C38 C41 10 F 0.1 F 0.001 F AVDD 10V RED DUTDRVDD DUTDRVDD 10V RED DVDD TP11 TP12 TP13 TP14 BLK BLK BLK BLK AD9226LQFP 3 28 OTR0 AVDD1 OTR 4 27 D130 AVDD2 MSB- AVSS1 B2 D120 2 25 D110 AVSS2 D100 SENSE ...
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... DUTCLK OTR JP4 JP3 2 AVDD C3 C10 10 F 0.1 F 10V U8 DECOUPLING AD9226 DVDD RP1 RP1 RP1 RP1 RP1 ...
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... AD9226 RP3 OTRO OTR RP3 D130 D13 RP3 D120 D12 RP3 D110 D11 RP4 C15 AVDD 10 F D100 D10 RP4 10V D90 D9 RP4 C69 0.1 F D80 D8 RP4 R37 D70 D7 499 3 R34 VCC ...
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... AD9226 28-Lead Shrink Small Outline (RS-28) 0.407 (10.34) 0.397 (10.08 0.07 (1.79) 0.078 (1.98) PIN 1 0.066 (1.67) 0.068 (1.73) 0.0256 0.015 (0.38) 0.008 (0.203) SEATING 0.009 (0.229) (0.65) 0.010 (0.25) PLANE 0.002 (0.050) BSC 0.005 (0.127) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead Thin Plastic Quad Flatpack 0.063 (1.60) 0.030 (0.75) 0.018 (0.45) COPLANARITY 0 ...