AD6644 Analog Devices, AD6644 Datasheet - Page 13
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AD6644
Manufacturer Part Number
AD6644
Description
14-Bit, 40 MSPS/65 MSPS Analog-to-Digital Converter
Manufacturer
Analog Devices
Datasheet
1.AD6644.pdf
(24 pages)
Specifications of AD6644
Resolution (bits)
14bit
# Chan
1
Sample Rate
65MSPS
Interface
Par
Analog Input Type
Diff-Uni
Ain Range
2.2 V p-p
Adc Architecture
Pipelined
Pkg Type
QFP
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TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating the
input phase 180° and taking the peak measurement again. The
difference is then computed between both peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Encode Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the
ENCODE pulse should be left in the Logic 1 state to achieve
rated performance; pulse width low is the minimum time
ENCODE pulse should be left in a low state. Optimum
performance is achieved using a 50% duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
POWER
Full
Scale
=
10
log
⎡
⎢
⎢
⎢
⎢
⎢
⎣
V
2
Full
Z
. 0
−
001
Input
Scale
rms
⎤
⎥
⎥
⎥
⎥
⎥
⎦
Rev. D | Page 13 of 24
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least-square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Noise (for Any Range Within the ADC)
where:
Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value for the particular input level.
Signal is the signal level within the ADC reported in dB below
full scale.
V
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE , and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc.
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
NOISE
V
includes both thermal and quantization noise.
NOISE
=
Z
×
. 0
001
×
10
⎛
⎜
⎝
FS
dBm
−
SNR
dBc
10
−
Signal
AD6644
dBFS
⎞
⎟
⎠