AD7476 Analog Devices, AD7476 Datasheet
AD7476
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AD7476 Summary of contents
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... DSPs. The input signal is sampled on the falling edge of CS and the conversion is initiated at this point. There are no pipeline delays associated with these parts. The AD7476/AD7477/AD7478 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the parts is taken internally from V allows the widest dynamic input range to the ADC ...
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... Ordering Guide .......................................................................... 22 3/04—Rev Rev. D Added U.S. Patent Number .............................................................. 1 Changes to Specifications ................................................................. 2 Changes to Absolute Maximum Ratings ........................................ 6 Changes to AD7476/AD7477/AD7478 to ADSP-21xx Interface section .............................................................................. 16 2/03—Rev Rev. C Changes to General Description ..................................................... 1 Changes to Specifications ................................................................. 2 Changes to Absolute Maximum Ratings ........................................ 6 Changes to Ordering Guide ............................................................. 6 Changes to Typical Connection Diagram section ..................... 10 Changes to Figure 8 caption ...
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... SPECIFICATIONS AD7476 SPECIFICATIONS A version 2 5. MHz SCLK MHz 600 kSPS, unless otherwise noted; T SCLK SAMPLE Table 1. Parameter DYNAMIC PERFORMANCE 3 Signal-to-(Noise + Distortion) (SINAD) 3 Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) 3 Peak Harmonic or Spurious Noise (SFDR) 3 Intermodulation Distortion (IMD) ...
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... AD7476/AD7477/AD7478 Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation 7 Normal Mode (Operational) Full Power-Down 1 Temperature range for A and B versions is −40°C to +85°C; temperature range for S version is −55°C to +125°C. ...
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... DD DD 0.4 0.4 ±10 ± Straight (Natural) Binary 800 800 400 400 1 1 Rev Page AD7476/AD7477/AD7478 Unit Test Conditions/Comments f = 100 kHz sine wave SAMPLE dB min dB max dB max dB typ fa = 103.5 kHz 113.5 kHz dB typ fa = 103.5 kHz 113.5 kHz ns typ ps typ MHz typ ...
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... AD7476/AD7477/AD7478 Parameter POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode 5 Power Dissipation Normal Mode (Operational) Full Power-Down 1 Temperature range for A version is −40°C to +85°C; temperature range for S version is −55°C to +125°C. 2 Operational from V = 2.0 V, with input high voltage, V ...
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... Rev Page AD7476/AD7477/AD7478 Unit Test Conditions/Comments f = 100 kHz sine wave SAMPLE dB min dB max dB max dB typ fa = 498.7 kHz 508.7 kHz dB typ fa = 498.7 kHz 508.7 kHz ns typ ps typ MHz typ @ 3 dB Bits LSB max ...
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... DD 2 Guaranteed by characterization. All input signals are specified with (10 Version A timing specifications apply to the AD7477 and AD7478 S version; B version timing specifications apply to the AD7476 S version. 4 Mark/space ratio for the SCLK input is 40/60 to 60/40. 5 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0 2.0 V. ...
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... maximum rating conditions for extended periods may affect −0 0 device reliability. 1 ±10 mA –40°C to +85°C −55°C to +125°C −65°C to +150°C 150°C 230°C/W 92°C/W 235 (0/+5)°C 255 (0/+5)°C 3.5 kV Rev Page AD7476/AD7477/AD7478 ...
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... Data Out. Logic output. The conversion result is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7476 consists of four leading zeros followed by the 12 bits of conversion data; this is provided MSB first. The data stream from the AD7477 consists of four leading zeros followed by the 10 bits of conversion data, followed by two trailing zeros, which is also provided MSB first ...
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... INPUT FREQUENCY (kHz) Figure 8. AD7476 SINAD vs. Input Frequency at 993 kSPS –69.0 SCLK = 12MHz –69.5 –70.0 –70.5 –71.0 –71.5 –72.0 –72.5 10k 100k INPUT FREQUENCY (kHz) Figure 9. AD7476 SINAD vs. Input Frequency at 605 kSPS = 1MSPS = 100kHz 400 450 500 4.75V ...
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... AGND + 1 LSB). Gain Error For the AD7476/AD7477, this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (such as V – 1.5 LSB) after the offset error has been adjusted out. For ...
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... For the AD7476/AD7477, designed code transitions occur midway between successive integer LSB values, such as ½ external DD LSB, 1½ LSB, and so on. The LSB size for the AD7476 is V /4096, and the LSB size for the AD7477 ideal transfer characteristic for the AD7476/AD7477 is shown in Figure 12 ...
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... MSPS, the REF193 needs to supply a maximum of 1 the AD7476/AD7477/AD7478. The load regulation of the REF193 is typically 10 ppm/mA (REF193, V results in an error of 16 ppm (48 μV) for the 1.6 mA drawn from it. This corresponds to a 0.065 LSB error for the AD7476 with from the REF193, a 0.016 LSB error for the DD AD7477, and a 0 ...
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... This mode is intended for fastest throughput rate performance. = 993 kSPS s Users do not have to worry about power-up times with the AD7476/AD7477/AD7478 remaining fully powered at all times. Figure 19 shows the general diagram of the AD7476/AD7477 2.35V DD AD7478 in normal mode. The conversion is initiated on the falling edge de- ...
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... SCLK SDATA INVALID DATA To exit this mode of operation and power up the AD7476/ AD7477/AD7478 again, perform a dummy conversion. On the falling edge the device begins to power up, and continues to power up as long held low until after the falling edge of the tenth SCLK. The device is fully powered up once 16 SCLKs have elapsed and, as shown in results from the next conversion ...
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... SCLK falling edge and brought low again after a time initiate the conversion. QUIET When power supplies are first applied to the AD7476/AD7477/ AD7478, the ADC may power up in either power-down mode or normal mode. Allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. ...
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... ZERO ZERO 4 LEADING ZEROS Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7476/ AD7477/AD7478. CS going low provides the first leading zero to be read by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges, beginning with the second leading zero ...
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... AD7476/ AD7477/ AD7478 AD7476/AD7477/AD7478 to DSP56xxx Interface The connection diagram in Figure 28 shows how the AD7476/ AD7477/AD7478 can be connected to the synchronous serial interface (SSI) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in synchronous mode (SYN bit in CRB =1) with internally generated word frame sync for both Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in CRB) ...
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... SC2 1 ADDITIONAL PINS OMITTED FOR CLARITY Figure 28. Interfacing to the DSP56xxx AD7476/AD7477/AD7478 to MC68HC16 Interface The serial peripheral interface (SPI) on the MC68HC16 is configured for master mode (MSTR = 1), the clock polarity bit (CPOL and the clock phase bit (CPHA The SPI is configured by writing to the SPI Control Register (SPCR). For more information on the MC68HC16, check with Motorola for the related documentation ...
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... OUTLINE DIMENSIONS INDICATOR 0.15 MAX 2.90 BSC 2.80 BSC 1.60 BSC PIN 1 0.95 BSC 1.90 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 0.50 SEATING 0.30 PLANE COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 30. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters Rev Page AD7476/AD7477/AD7478 10° 0.60 4° 0.45 0° 0.30 ...
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... This board is a complete unit allowing control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, users need to order the particular ADC evaluation board, such as the EVAL-AD7476CB, the EVAL-CONTROL BRD2, and transformer. See relevant evaluation board application note for more information ...
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... NOTES AD7476/AD7477/AD7478 Rev Page ...
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... AD7476/AD7477/AD7478 NOTES ©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01024-0-1/09(F) Rev Page ...