AD9225 Analog Devices, AD9225 Datasheet - Page 13

• Manufacturer Part Number: AD9225
• Description: 12-Bit , 25 MSPS Monolithic A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9225

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 25MSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,2 V p-p,4 V p-p,Uni (Vref) x 2,Uni 2.0V,Uni 4.0V
• Adc Architecture: Pipelined
• Pkg Type: SOIC,SOP

Rev. C
Op Amp with DC Level Shifting
Figure 9 shows a dc-coupled level shifting circuit employing an op
amp, A1, to sum the input signal with the desired dc set. Configur-
ing the op amp in the inverting mode with the given resistor values
results in an ac signal gain of –1. If the signal inversion is undesir-
able, interchange the VINA and VINB connections to re-establish
the original signal polarity. The dc voltage at VREF sets the
common-mode voltage of the AD9225. For example, when
VREF = 2.0 V, the input level from the op amp will also be cen-
tered around 2.0 V. The use of ratio matched, thin-film resistor
networks will minimize gain and offset errors. Also, an optional
pull-up resistor, RP, may be used to reduce the output load on
VREF to less than its 1 mA maximum.
AC COUPLING AND INTERFACE ISSUES
For applications where ac coupling is appropriate, the op amp
output can be easily level-shifted via a coupling capacitor. This has
the advantage of allowing the op amp common-mode level to be
symmetrically biased to its midsupply level (i.e., (V
Op amps that operate symmetrically with respect to their power
supplies typically provide the best ac performance as well as great-
est input/output span. Various high speed/performance amplifiers
which are restricted to +5 V/–5 V operation and/or specified for
+5 V single-supply operation can be easily configured for the 4 V
or 2 V input span of the AD9225. Note that differential trans-
former coupling, which is another form of ac coupling, should be
considered for optimum ac performance.
Simple AC Interface
Figure 10 shows a typical example of an ac-coupled, single-ended
configuration. The bias voltage shifts the bipolar, ground-refer-
enced input signal to approximately AVDD/2. The value for C1
and C2 will depend on the size of the resistor, R. The capacitors,
C1 and C2, are a 0.1 mF ceramic and 10 mF tantalum capacitor in
parallel to achieve a low cutoff frequency while maintaining a low
Figure 9. Single-Ended Input with DC-Coupled Level Shift
–VREF
+VREF
VREF
Figure 8. Single-Ended AD9225 Op Amp Drive Circuit
4V
0V
+V
**OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE
*OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D
R
P
**
0V
0.1 F
500 *
DC
–V
+V
U1
500 *
500 *
3
2
10 F
2.0V
A1
+V
R
7
4
CC
S
0.1 F
NC
NC
500 *
1
5
0.1 F
6
R
S
R
R
S
S
VINA
VINB
VREF
SENSE
CC
AD9225
VINB
VINA
+ V
AD9225
EE
)/2).
–13–
impedance over a wide frequency range. The combination of the
capacitor and the resistor form a high-pass filter with a high-pass –
3 dB frequency determined by the equation
The low impedance VREF voltage source biases both the VINB
input and provides the bias voltage for the VINA input. Figure 10
shows the VREF configured for 2.0 V thus the input range of the
ADC is 0 V to 4 V. Other input ranges could be selected by chang-
ing VREF.
Alternative AC Interface
Figure 11 shows a flexible ac-coupled circuit that can be config-
ured for different input spans. Since the common-mode voltage of
VINA and VINB are biased to midsupply independent of VREF,
VREF can be pin strapped or reconfigured to achieve input spans
between 2 V and 4 V p-p. The AD9225’s CMRR along with the
symmetrical coupling R-C networks will reject both power supply
variations and noise. The resistors, R, establish the common-mode
voltage. They may have a high value (e.g., 5 kW) to minimize
power consumption and establish a low cutoff frequency. The
capacitors, C1 and C2, are typically a 0.1 mF ceramic and 10 mF
tantalum capacitor in parallel to achieve a low cutoff frequency
while maintaining a low impedance over a wide frequency range.
R
performance is achieved when VINA and VINB are driven via
symmetrical networks. The f
the equation
+2V
–2V
S
0V
isolates the buffer amplifier from the ADC input. The optimum
Figure 11. AC-Coupled Input-Flexible Input Span,
V
V
IN
CM
V
= 2.5 V
IN
f
–3 dB
–5V
+5V
Figure 10. AC-Coupled Input
f
AD9631
–3 dB
= 1/(2 ¥
0.1 F
10 F
=
C2
C1
0.1 F
10 F
2 p ¥ 6K +(C1+ C2)
C2
C1
C1
10 F
C3
0.1 F
0.1 F
–3 dB
¥ R ¥ (C1 + C2))
4.5
2.5
0.5
point can be approximated by
1k
1k
1
C2
0.1 F
10 F
R
R
+V
S
S
R
R
+V
VINA
VCM
VINB
R
R
AD9225
AD9225
R
R
S
S
VINA
VINB
AD9225