AD7827 Analog Devices, AD7827 Datasheet - Page 3

• Manufacturer Part Number: AD7827
• Description: 3/5V, 1 MSPS, 8-Bit, Serial Interface Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7827

• Resolution (bits): 8bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni 2.0V,Uni 2.5V
• Adc Architecture: Pipelined
• Pkg Type: DIP,SOIC

TIMING CHARACTERISTICS
Parameter
POWER SUPPLY
NOTES
1
2
Specifications subject to change without notice.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
Specifications subject to change without notice.
REV. 0
See Terminology section of this data sheet.
Refer to the Analog Input section for an explanation of the Analog Input(s).
Sample tested to ensure compliance.
See Figures 13, 14 and 15.
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V with V
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
CONVERT
1
2
3
4
5
6
7
8
9
10
11
POWER-UP
POWER-UP
output to cross 0.4 V or 2.0 V with V
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
the part and as such is independent of external bus loading capacitances.
3
3
3
4
V
I
Power Dissipation
DD
DD
Normal Operation
Power-Down
Normal Operation
Power-Down
200 kSPS
1 MSPS
5 V
420
20
t
t
14
14
20
14
25
25
20
35
20
30
1
25
CONVERT
CONVERT
10%
+t
+t
3
3
+t
7
+t
DD
8
Figure 1. Load Circuit for Digital Output Timing Specifications
= 3 V
3 V
420
20
t
t
18
18
20
18
25
25
20
35
20
30
1
25
CONVERT
CONVERT
10%.
1, 2
10%
+t
+t
(V
3
3
REFIN/REFOUT
+t
Version B
4.5
5.5
2.7
3.3
10
1
30
9.58
47.88
OUTPUT
7
+t
PIN
TO
8
= 2.5 V, all specifications –40 C to +105 C, unless otherwise noted)
Units
ns max
ns min
ns min
ns max
ns max
ns max
ns max
ns max
ns min
ns min
ns min
ns max
ns max
ns min
50pF
s max
s max
C
L
200 A
200 A
–3–
Units
V min
V max
V min
V max
mA max
mW max
mW max
mW max
A max
Conditions/Comments
Conversion Time.
Minimum CONVST Pulsewidth.
Falling edge of CONVST to falling edge of RFS.
Rising edge of SCLK to falling edge of RFS.
Rising edge of SCLK to rising edge of RFS.
Rising edge of SCLK to high impedance disabled.
Rising edge of SCLK to D
Minimum high SCLK pulse duration.
Minimum low SCLK pulse duration.
Bus relinquish time after SCLK falling edge.
Maximum delay from falling edge CONVST to rising edge RFS if
RFS reset by CONVST.
Minimum time between end of serial read and next falling edge of
CONVST.
Power-up time from rising edge of CONVST using external 2.5 V
reference.
Power-up time from rising edge of CONVST using on-chip reference.
I
I
OL
OH
9
, quoted in the timing characteristics is the true bus relinquish time of
+2.1V
Test Conditions/Comments
5 V
3 V
8 mA Typically
Logic Inputs = 0 V or V
V
Typically 24 mW
DD
OUT
= 3 V
10% For Specified Performance
10% For Specified Performance
DD
valid delay.
= 5 V
10% and time required for an
DD
AD7827