AD7864 Analog Devices, AD7864 Datasheet
AD7864
Specifications of AD7864
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AD7864 Summary of contents
Page 1
... HW/SW select of channel sequence for conversion Single-supply operation Selection of input ranges ±10 V, ±5 V for AD7864-1 ±2.5 V for AD7864 2 for AD7864-2 High speed parallel interface that allows Interfacing processors Low power typical Power saving mode, 20 μW typical ...
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... B to Rev. C Updated Format .................................................................. Universal Changes to t Timing Parameter, Table 2....................................... 5 5 Changes to Figure 15 ...................................................................... 20 Changes to AD7864 to MC68HC000 Interface Section ............ 24 Changes to Figure 25 ...................................................................... 24 Updated Outline Dimensions ....................................................... 29 Changes to Ordering Guide .......................................................... 29 Standby Mode Operation .......................................................... 18 Accessing the Output Data Registers ....................................... 18 Offset and Full-Scale Adjustment ................................................ 20 Positive Full-Scale Adjust ...
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... AD7864-2 3 Positive Gain Error 3 Positive Gain Error Match Unipolar Offset Error Unipolar Offset Error Match ANALOG INPUTS AD7864-1 Input Voltage Range Input Resistance AD7864-3 Input Voltage Range Input Resistance = internal, clock = internal; all specifications T REF 1 A Version B Version Unit 3 3 MHz typ ...
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... IN LOGIC OUTPUTS Output High Voltage Output Low Voltage DB11 to DB0 High Impedance Leakage Current 4 Capacitance Output Coding AD7864-1, AD7864-3 AD7864-2 CONVERSION RATE Conversion Time 2, 3 Track-And-Hold Acquisition Time Throughput Time POWER REQUIREMENTS Normal Mode Standby Mode ...
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... Input data hold time 1.6mA TO OUTPUT 50pF 400µA Figure 2. Load Circuit for Access Time and Bus Relinquish Time Rev Page unless otherwise noted. MIN MAX + EOC pulse CONV = 5 V DRIVE = 3 V DRIVE = 5 V DRIVE = 3 V DRIVE pin. REF 1.6V AD7864 1, 2 ...
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... Parameter AV to AGND DGND DD AGND to DGND Analog Input Voltage to AGND AD7864-1 (±10 V Input Range) AD7864-1 (±5 V Input Range) AD7864-3 AD7864-2 Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND V to AGND DRIVE V to DGND DRIVE ...
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... Logic 0. The selection is latched on the rising edge of CONVST . See the 11 Hardware/Software Select Input. When this pin is at Logic 0, the AD7864 conversion sequence selection SEL controlled via the SL1 to SL4 input pins. When this pin is at Logic 1, the sequence is controlled via the channel select register ...
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... Conversion Clock Input. This is an externally applied clock that allows the user to control the conversion rate of the AD7864. Each conversion needs 14 clock cycles for the conversion to be completed and an EOC pulse to be generated. The clock should have a duty cycle that is no worse than 60/40. See the section ...
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... V range), after the bipolar offset error has been adjusted out. Positive Full-Scale Error (AD7864- 2.5 V and This is the deviation of the last code transition (11...110 to 11...111) from the ideal 2 × REF unipolar offset error has been adjusted out. ...
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... AD7864 It means that the user must wait for the duration of the track- and-hold acquisition time after the end of conversion or after a step input change before starting another INxA INxB conversion to ensure that the part operates to specification. Rev Page ...
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... V, (AD7864-1 ±10 V range), − +20 V (AD7864-1 ±5 V range), − +20 V (AD7864-2), and − +20 V (AD7864-3), without causing damage. The AD7864 has two operating modes: reading-between-conversions and reading- after-the-conversion sequence ...
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... If the application requires a reference with a tighter tolerance or the AD7864 needs to be used with a system reference, the user has the option of connecting an external reference to this V pin. The external reference effectively overdrives the internal reference and thus provides the reference source for the ADC ...
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... The V and INxA INxA range, with LSB = FSR/4096 = 4.883 mV (±10 V for the AD7864-1) and 2.441 mV (±5 V for the AD7864-1) with V input while the INxB AD7864-2 Figure 5 shows the analog input section of the AD7864-2. Each input can be configured for operation 2.5 V AD7864-1 operation ...
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... AGND + 3/2 LSB 000...001 to 000...010 AGND + 1/2 LSB 000...000 to 000...001 1 FSR is the full-scale range and 2.5 V and for the AD7864-2 with V = 2.5 V. REF 2 1 LSB = FSR/4096 and is 0. 2.5 V) and 1. for the AD7864-2 with ...
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... EOC going logic low, another option is to tie the EOC and RD pins together and use the rising edge of EOC to latch the conversion result. Although the AD7864 has some special features that permit reading during a conversion (such as a separate supply for the output data drivers, V that the read operation be completed when EOC is logic low, that is, before the start of the next conversion ...
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... AD7864 logic high). The pointer is incremented to point to the next register (next conversion result) when that conversion result is available. Thus, FRSTDATA in Figure 9 is shown as going low just prior to the second EOC pulse. Repeated read operations during a conversion continue to access the data at the current pointer location until the pointer is incremented at the end of that conversion ...
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... In some instances, however, it may be useful to use an external clock when high throughput rates are not required. For example, two or more AD7864s can be synchronized by using the same external clock for all devices. In this way, there is no latency between output logic signals like EOC due to differences in the frequency of the internal clock oscillators ...
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... The maximum throughput rate that can be achieved when powering down between conversions is 1/(t 2 μs) = 100 kSPS, approximately. When operating the AD7864 in a standby mode between conversions, the power savings can be significant. For example, with a throughput rate of 10 kSPS, the AD7864 is powered down ( μ ...
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... OE NO. 3 POINTER* IN4 NOT VALID OE NO. 4 RESET AD7864 Figure 14. Output Data Registers Rev Page Reading Between Each Conversion in the subsection within the Selecting a section. The pointer is reset to point RD signal when the last FRSTDATA V DRIVE OUTPUT DRIVERS DB0 TO DB11 OE AD7864 ...
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... Where adjustment is required, offset error must be adjusted before full-scale error. This is achieved by trimming the offset of the op amp driving the analog input of the AD7864 while the input voltage is 1/2 LSB below analog ground. The trim procedure is as follows: apply a voltage of −2.44 mV (−1/2 LSB adjust the op amp offset voltage until the ADC output code flickers between 1111 1111 1111 and 0000 0000 0000 ...
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... SNR data can be obtained. Figure 17 shows a typical 4096 point FFT plot of the AD7864 with an input signal of 99.9 kHz and a sampling frequency of 500 kHz. The SNR obtained from this graph is 72.6 dB. Note that the harmonics are taken into account when calculating the SNR ...
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... Therefore, by measuring the overall SNR performance (including noise due to jitter, system, and quantization) of the AD7864, a good estimation of the jitter performance of the AD7864 can be calculated ...
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... From Figure 22, the ENOB of the AD7864 at 1 MHz is approximately 11 bits. This is equivalent SNR. SNR = SNR + SNR = 68 dB TOTAL JITTER QUANT SNR + 72 dB (at 100 kHz) JITTER SNR = 70.2 dB JITTER From Equation 3 70 × log [1/(2 × π × 1 MHz × σ)] 10 σ where σ ...
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... This maps the AD7864 into external data memory. The RD signal from the TMS320C5x is used to enable the ADC data onto the data bus. The AD7864 has a fast parallel bus, consequently there are no wait state requirements. The following instruction is used to read the ...
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... D0 TO D15 control applications. A block diagram of a vector motor control application using the AD7864 is shown in Figure 26. The position of the field is derived by determining the current in each phase of the motor. Only two phase currents need to be measured because the third can be calculated if two phases are known. V AD7864 are used to digitize this information ...
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... AD7864 MULTIPLE AD7864S IN A SYSTEM Figure 27 shows a system where a number of AD7864s are configured to handle multiple input channels. This type of configuration is common in applications such as sonar and radar. The AD7864 is specified with maximum limits on aperture delay match. This means that the user knows the difference in the sampling instant between all channels ...
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... This board is a complete unit, allowing control and communicate with all Analog Devices, Inc., evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board needs to be ordered, for example, EVAL-AD7864-1CB, the EVAL-CONTROL BRD2, and transformer ...
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... AD7864 NOTES ©1998–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01341-0-2/09(D) Rev Page ...