AD7825 Analog Devices, AD7825 Datasheet - Page 13
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AD7825
Manufacturer Part Number
AD7825
Description
3 V/5 V, 2 MSPS, 8-Bit, 1-/4-/8-Channel Sampling ADCs
Manufacturer
Analog Devices
Datasheet
1.AD7822.pdf
(28 pages)
Specifications of AD7825
Resolution (bits)
8bit
# Chan
4
Sample Rate
2MSPS
Interface
Par
Analog Input Type
SE-Uni
Ain Range
2 V p-p,2.5V p-p
Adc Architecture
Pipelined
Pkg Type
DIP,SOIC,SOP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7825BRUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7825BRZ
Manufacturer:
ADI/亚德诺
Quantity:
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Capacitor C2 in Figure 15 is typically about 4 pF and can be
primarily attributed to pin capacitance. The resistor, R1, is a
lumped component made up of the on resistance of several
components, including that of the multiplexer and the track-
and-hold. This resistor is typically about 310 Ω. Capacitor C1
is the track-and-hold capacitor and has a capacitance of 0.5 pF.
Switch 1 is the track-and-hold switch, and Switch 2 is that of the
sampling capacitor, as shown in Figure 6 and Figure 7.
When in track phase, Switch 1 is closed and Switch 2 is in
Position A. When in hold mode, Switch 1 opens and Switch 2
remains in Position A. The track-and-hold remains in hold
mode for 120 ns (see the Circuit Description section), after
which it returns to track mode and the ADC enters its conversion
phase. At this point, Switch 1 opens and Switch 2 moves to
Position B. At the end of the conversion, Switch 2 moves back
to Position A.
Analog Input Selection
On power-up, the default V
to normal operation from power-down, the V
same one that was selected prior to initiation of power-down.
Table 6 shows the multiplexer address corresponding to each
analog input from V
Table 6.
A2
0
0
0
0
1
1
1
1
Channel selection on the AD7825 and AD7829 is made without
the necessity of a write operation. The address of the next channel
to be converted is latched at the start of the current read operation,
that is, on the falling edge of RD while CS is low, as shown in
Figure 16. This allows for improved throughput rates in “channel
hopping” applications.
V
IN
4pF
C2
A1
0
0
1
1
0
0
1
1
Figure 15. Equivalent Analog Input Circuit
V
DD
0
1
0
1
0
1
0
1
A0
D1
D2
IN1
to V
310Ω
R1
IN4(8)
Analog Input Selected
V
V
V
V
V
V
V
V
IN
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
selection is V
for the AD7825 or AD7829.
SW1
0.5pF A
C1
IN1
. When returning
SW2
IN
selected is the
B
Rev. C | Page 13 of 28
DB0 TO DB7
There is a minimum time delay between the falling edge of RD
and the next falling edge of the CONVST signal, t
minimum acquisition time required of the track-and-hold to
maintain 8-bit performance. Figure 17 shows the typical perform-
ance of the AD7825 when channel hopping for various acquisition
times. These results are obtained using an external reference
and internal V
with 0 V on Channel 4 and 0.5 V on Channel 1.
The on-chip track-and-hold can accommodate input frequencies
to 10 MHz, making the AD7822/AD7825/AD7829 ideal for
subsampling applications. When the AD7825 is converting a
10 MHz input signal at a sampling rate of 2 MSPS, the effective
number of bits typically remains above seven, corresponding to
a signal-to-noise ratio of 42 dBs, as shown in Figure 18.
A0 TO A2
CONVST
TRACK CHx
Figure 17. Effective Number of Bits vs. Acquisition Time for the AD7825
EOC
RD
CS
8.0
7.5
7.0
6.5
6.0
5.5
5.0
8.5
500
t
2
HOLD CHx
MID
200
120ns
Figure 16. Channel Hopping Timing
while channel hopping between V
100
t
1
ACQUISITION TIME (ns)
AD7822/AD7825/AD7829
50
TRACK CHx
40
ADDRESS CHANNEL y
30
TRACK CHy
VALID
DATA
20
t
13
15
t
13
3
. This is the
IN1
HOLD CHy
and V
10
IN4