AD7730 Analog Devices, AD7730 Datasheet

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... APPLICATIONS Weigh Scales Pressure Measurement GENERAL DESCRIPTION The AD7730 is a complete analog front end for weigh-scale and pressure measurement applications. The device accepts low- level signals directly from a transducer and outputs a serial digital word. The input signal is applied to a proprietary pro- grammable gain front end based around an analog modulator ...

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... AD7730–SPECIFICATIONS Parameter STATIC PERFORMANCE (CHP = Missing Codes 2 Output Noise and Update Rates Integral Nonlinearity 2 Offset Error 2 Offset Drift vs. Temperature 4 Offset Drift vs. Time 2, 5 Positive Full-Scale Error Positive Full-Scale Drift vs Temp 4 Positive Full-Scale Drift vs Time 2, 8 Gain Error Gain Drift vs ...

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... Typically 10 A. External MCLK max All Input Ranges Except +10 mV and 10 mV 125 mW max Input Ranges +10 mV and 10 mV Only 125 W max Typically 50 W. External MCLK –3– AD7730/AD7730L = + ...

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... AD7730/AD7730L NOTES 11 Temperature range: – + Sample tested during initial release. 13 The offset (or zero) numbers with CHP = 1 are typically 3 V precalibration. Internal zero-scale calibration reduces this by about 1 V. Offset numbers with CHP = 0 can precalibration. Internal zero-scale calibration reduces this typical. System zero-scale calibration reduces offset numbers with CHP = 1 and CHP = 0 to the order of the noise ...

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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7730 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... FACILITATES RATIOMETRIC UNIPOLAR AND FOUR BIPOLAR OPERATION. THE REFERENCE INPUT RANGES FROM VOLTAGE CAN BE SELECTED TO +10mV TO +80mV BE NOMINALLY +2.5V OR +5V SEE PAGE 24 SEE PAGE 25 DV REF IN(–) REF IN(+) DD AD7730 REFERENCE DETECT AV DD SIGMA-DELTA A/D CONVERTER SIGMA- DELTA + MODULATOR PGA +/– BUFFER 6-BIT ...

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... Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer serial data to or from the AD7730. This serial clock can be a continuous clock with all data transmitted in a con- tinuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the AD7730 in smaller batches of data ...

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... If the active edge for the processor is a low-to-high SCLK transition, this input should be high. In this mode, the AD7730 puts out data on the DATA OUT line in a read operation on a high-to-low transi- tion of SCLK and clocks in data from the DATA IN line in a write operation on a low-to-high transition of SCLK ...

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... Logic Output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a logic low on this output indicates that a new output word is available from the AD7730 data register. The RDY pin will return high upon completion of a read operation of a full output word data read has taken place after an output update, the RDY line will return high prior to the next output update, remain high while the update is taking place and return low again ...

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... This mode is the primary mode of operation of the device. Table I shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7730 when used in chopping mode (CHP of Filter Register = 1) with a master clock frequency of 4.9152 MHz. These numbers are typical and are generated at a differential analog input voltage The output update rate is selected via the SF0 to SF11 bits of the Filter Register ...

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... Hz 512 41.6 ms 1200 Hz 46.8 Hz 256 20.8 ms ON-CHIP REGISTERS The AD7730 contains thirteen on-chip registers which can be accessed via the serial port of the part. These registers are summarized in Figure 4 and in Table V and described in detail in the following sections. DIN DOUT DOUT DOUT DOUT DOUT DOUT ...

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... AD7730/AD7730L Register Name Type Size Communications Write Only 8 Bits Register WEN ZERO RW1 RW0 ZERO Status Register Read Only 8 Bits RDY STDY STBY NOREF MS3 Data Register Read Only 16 Bits or 24 Bits Mode Register Read/Write 16 Bits B/U MD2 MD1 MD0 DEN HIREF ...

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... Communications Register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high, returns the AD7730 to this default state by resetting the part. Table VI outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denot- ing the bits are in the Communications Register ...

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... Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first bit of the data stream. Figure 5 shows a flowchart for reading from the registers on the AD7730. The number in brackets indicates the power-on/reset default status of that bit. ...

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... The Data Register on the part is a read-only register which contains the most up-to-date conversion result from the AD7730. Fig- ure 5 shows a flowchart for reading from the registers on the AD7730. The register can be programmed to be either 16 bits or 24 bits wide, determined by the status of the WL bit of the Mode Register. The RDY output and RDY bit of the Status Register are set low when the Data Register is updated ...

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... Single Conversion Mode. In this mode, the AD7730 performs a single conversion, updates the Data Register, returns to the Sync Mode and resets the mode bits The result of the single conversion on the AD7730 in this mode will not be provided until the full settling time of the filter has elapsed. 0 ...

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... MCLK OUT as a clock source for other devices in the system or of turning off the MCLK OUT as a power saving feature. When using an external master clock at the MCLK IN pin, the AD7730 contin- ues to have internal clocks and will convert normally with the CLKDIS bit active. When using a crystal oscillator or ceramic resonator across the MCLK IN and MCLK OUT pins, the AD7730 clock is stopped and no conversions take place when the CLKDIS bit is active ...

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... FR denoting the bits are in the Filter Register. FR23 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7730 and Figure 6 shows a flowchart for writing to the registers on the part. ...

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... FR5 AC AC Excitation Bit. If the signal source to the AD7730 is ac-excited must be placed in this bit. For dc-excited inputs, this bit must be 0. The ac bit has no effect if CHP is 0. With the ac bit at 1, the AD7730 assumes that the voltage at the AIN(+)/AIN(–) and REF IN(+)/REF IN(–) input terminals are reversed on alternate input sampling cycles (i ...

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... RESET) status of all 0s as the part will be placed in one of its test modes and will not operate correctly. If the part enters one of its test modes, exercising RESET or writing 32 successive 1s to the part will exit the AD7730 from the mode and return all register contents to their power-on/reset status ...

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... READING FROM AND WRITING TO THE ON-CHIP REGISTERS The AD7730 contains a total of thirteen on-chip registers. These registers are all accessed over a three-wire interface result, addressing of registers is via a write operation to the topmost register on the part, the Communications Register. Figure 5 shows a flowchart for reading from the different registers on the part summarizing the sequence and the words to be written to access each of the registers ...

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... AD7730/AD7730L CALIBRATION OPERATION SUMMARY The AD7730 contains a number of calibration options as outlined previously. Table XVII summarizes the calibration types, the operations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to monitor the hardware RDY pin using either interrupt-driven or polling routines. The second method software poll of the RDY bit in the Status Register ...

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... CIRCUIT DESCRIPTION The AD7730 is a sigma-delta A/D converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low-frequency signals such as those in weigh-scale, strain-gage, pressure transducer or temperature measurement applications. It contains a sigma-delta (or charge-balancing) ADC, a calibra- tion microcontroller with on-chip static RAM, a clock oscillator, a digital filter and a bidirectional serial communications port ...

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... Unipolar and bipolar signals on the AIN(+) input are referenced to the voltage on the respective AIN(–) input. For example, if AIN(–) is +2.5 V and the AD7730 is configured for an analog input range +10 mV with no DAC offset correction, the input voltage range on the AIN(+) input is +2 +2.51 V. Similarly, if AIN(– ...

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... AD7730 include the AD780, REF43 and REF192. If any of these references are used as the reference source for the AD7730, the HIREF bit should be set generally recommended to decouple the output of these references to further reduce the noise level. ...

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... FIR filter. The third option for the second stage filter is that it is completely bypassed so the only filtering provided on the AD7730 is the first stage. The various filter stages and options are discussed in the follow- ing sections. ...

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... The overall filter response of the AD7730 is guaranteed to have no overshoot. Figure 11 shows the full frequency response of the AD7730 when the second stage filter is set for normal FIR operation. This response is for chop mode enabled with the decimal equivalent of the word in the SF bits set to 512 and a master clock frequency of 4 ...

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... Hz signal. Similarly, multiples of the line frequency should be avoided as the output rate because harmonics of the line fre- quency will not be fully attenuated. The programmability of the AD7730’s output rate should allow the user to readily choose an output rate that overcomes this issue. An alternative is to use the part in nonchop mode. ...

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... CHP = 1, the output rms noise goes from 200 nV. With chopping disabled and SKIP mode enabled, each output from the AD7730 is a valid result in itself. However, with chop- ping enabled and SKIP mode enabled, the outputs from the AD7730 must be handled in pairs as each successive output is from reverse chopping polarities ...

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... The internal full-scale calibration is a two-step sequence that runs when an internal full-scale calibration command is written to the AD7730. One part of the calibration is a zero-scale cali- bration and as a result, the contents of the Offset Calibration Register are altered during this Internal Full-Scale Calibration. ...

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... CHP = 0, the duration is 24 1/Output Rate. At this time the MD2, MD1 and MD0 bits in the Mode Register return (Sync or Idle Mode for the AD7730). The RDY line goes high when calibration is initiated and returns low when calibration is complete. Note that the part has not performed a conversion at this time ...

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... IN and MCLK OUT pins, as per Figure 17. Capacitors C1 and C2 may or may not be required and may vary in value depend- ing on the crystal/resonator manufacturer's recommendations. The AD7730 has a capacitance MCLK IN and MCLK OUT so, in most cases, capacitors C1 and C2 will not be required to get the crystal/resonator operating at its cor- rect frequency. – ...

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... Data Register is updated. REV. A Reset Input The RESET input on the AD7730 resets all the logic, the digital filter and the analog modulator while all on-chip registers are AD7730 reset to their default state. RDY is driven high and the AD7730 ignores all communications to any of its registers while the RESET input is low ...

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... As a result, the AD7730 is more immune to noise interference than a conven- tional high resolution converter. However, because the resolu- tion of the AD7730 is so high and the noise levels from the AD7730 so low, care must be taken with regard to grounding and layout. ...

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... POL input is low. For POL = 1, the first falling edge of SCLK clocks data from the microcontrol- ler onto the DIN line of the AD7730 then clocked into the input shift register on the next rising edge of SCLK. For POL = 0, the first clock edge that clocks data from the microcontroller onto the DIN line of the AD7730 is a rising edge ...

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... Unlike microcontroller applica- tions, the DSP does not provide a clock edge to clock the MSB from the AD7730. In this case, the CS of the AD7730 places the MSB on the DOUT line. For processors with the rising edge of SCLK as the active edge, the POL input should be tied high. ...

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... CONFIGURING THE AD7730 The AD7730 contains twelve on-chip registers that can be accessed via the serial interface. Figure 5 and Figure 6 have outlined a flowchart for the reading and writing of these registers. Table XIX and Table XX outline sample pseudo-code for some commonly used routines. The required operating conditions will dictate the values loaded to the Mode, Filter and DAC Registers. The values given here are for example purposes only ...

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... For systems where it is preferable that the SCLK idle high, the CPOL bit of the 68HC11 should be set to a Logic 1 and the POL input of the AD7730 should be hard- wired to a logic high. The AD7730 is not capable of full duplex operation. If the AD7730 is configured for a write operation, no data appears on the DATA OUT lines even when the SCLK input is active ...

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... The POL pin of the AD7730 is hardwired low. Because the SCLK from the ADSP-2105 is a continuous clock, the CS of the AD7730 must be used to gate off the clock once the transfer is complete. The CS for the AD7730 is active when either the RFS or TFS outputs from the ADSP-2105 are active ...

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... Figure 23. Typical Connections for DC-Excited Bridge Application can be used with the excitation voltage and analog ground con- nected local to the AD7730’s REF IN(+) and REF IN(–) termi- nals. Illustrating a major advantage of the AD7730, the 5 V excitation voltage for the bridge can be used directly as the refer- ence voltage for the AD7730, eliminating the need for precision matched resistors in generating a scaled-down reference ...

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... CHOP mode, care must be taken in choosing the output update rate so it does not result in reducing line frequency rejection (see DIGITAL FILTERING section). The input offset current on the AD7730 maximum which results in a maxi- mum, dc offset voltage of 1. 350 tion. Care should taken with inserting large source impedances on the reference input pins as these inputs are not buffered and the source impedances can result in gain errors ...

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... The example shown is a dc-excited bridge that is driven from 5 V supplies. In such a circuit, two issues must be addressed. The first is how to get the AD7730 to handle input voltages near or below ground and the second is how to take the 10 V excitation voltage which appears across the bridge and generate a suitable reference voltage for the AD7730 ...

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... APPENDIX A AD7730L SPECIFICATIONS –43– ...

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... ACX *Protected by U.S. Patent No: 5, 134, 401. Other Patent Applications Filed. GENERAL DESCRIPTION The AD7730L is a complete low power analog front-end for weigh-scale and pressure measurement applications. The device accepts low level signals directly from a transducer and outputs a serial digital word. The input signal is applied to a proprietary programmable gain front end based around an analog modula- tor ...

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... max DD 0.3 V min 0.65 V max –45– AD7730/AD7730L unless otherwise noted.) Conditions/Comments Offset Error and Offset Drift Refer to Both Unipolar Offset and Bipolar Zero Errors Measured with Zero Differential Voltage At DC. Measured with Zero Differential Voltage 10 SKIP = 0 Offset Error and Offset Drift Refer to Both ...

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... AD7730/AD7730L Parameter LOGIC INPUTS Input Current All Inputs Except SCLK and MCLK Input Low Voltage INL V , Input Low Voltage INL V , Input High Voltage INH SCLK Only (Schmitt Trigerred Input T– V T– V – T– V – T– ...

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... Data Valid to SCLK Edge Setup Time ns min Data Valid to SCLK Edge Hold Time ns min SCLK High Pulsewidth ns min SCLK Low Pulsewidth CS Rising Edge to SCLK Edge Hold Time ns min –47– AD7730/AD7730L CLK IN unless otherwise noted and timed from a voltage level of 1 limits. ...

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... Output Noise (CHP = 0) Table XXIII shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7730L when used in nonchopping mode (CHP of Filter Register = 0) with a master clock frequency of 2.4576 MHz. These numbers are typical and are generated at a differential analog input voltage ...

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... Peak-to-Peak Resolution in Counts (Bits) Settling Time Input Range Fast Mode = 80 mV 53.2 ms 85k (16. 82k (16.5) 26.6 ms 65k (16) 13.3 ms 45k (15.5) 6.63 ms 30k (15) –49– AD7730/AD7730L Input Range Input Range Input Range = 215 135 100 245 160 110 275 180 130 370 ...

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... CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Internal Zero-Scale Calibration . . . . . . . . . . . . . . . . . . . . 30 Internal Full-Scale Calibration . . . . . . . . . . . . . . . . . . . . . 30 System Zero-Scale Calibration . . . . . . . . . . . . . . . . . . . . . 31 System Full-Scale Calibration . . . . . . . . . . . . . . . . . . . . . 31 Span and Offset Limits . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power-Up and Calibration . . . . . . . . . . . . . . . . . . . . . . . . 32 Drift Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 USING THE AD7730 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Clocking and Oscillator Circuit . . . . . . . . . . . . . . . . . . . . 32 System Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Single-Shot Conversions . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Grounding and Layout ...

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... Thin Shrink Small Outline (RU-24) 0.311 (7.90) 0.303 (7.70 PIN 1 0.0433 (1.10) MAX 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) BSC 0.0075 (0.19) 0.0035 (0.090) –51– AD7730/AD7730L 0.325 (8.25) 0.195 (4.95) 0.300 (7.62) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.0291 (0.74) x 45° 0.0098 (0.25) 0.0500 (1.27) 8° 0° 0.0157 (0.40) 0.028 (0.70) 8° 0° 0.020 (0.50) ...

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