AD9241 Analog Devices, AD9241 Datasheet

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AD9241

Manufacturer Part Number
AD9241
Description
Complete 14-Bit, 1.25 MSPS Monolithic A/D Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9241

Resolution (bits)
14bit
# Chan
1
Sample Rate
1.25MSPS
Interface
Par
Analog Input Type
Diff-Uni,SE-Uni
Ain Range
(2Vref) p-p,2 V p-p,5V p-p,Uni (Vref) x 2,Uni 2.0V,Uni 5.0V
Adc Architecture
Pipelined
Pkg Type
QFP

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a
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PRODUCT DESCRIPTION
The AD9241 is a 1.25 MSPS, single supply, 14-bit analog-to-
digital converter (ADC). It combines a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid implementations at a fraction of the
power consumption and cost. It is a complete, monolithic ADC
with an on-chip, high performance, low noise sample-and-hold
amplifier and programmable voltage reference. An external refer-
ence can also be chosen to suit the dc accuracy and temperature
drift requirements of the application. The device uses a multistage
differential pipelined architecture with digital output error correc-
tion logic to guarantee no missing codes over the full operating
temperature range.
The input of the AD9241 is highly flexible, allowing for easy
interfacing to imaging, communications, medical, and data-
acquisition systems. A truly differential input structure allows
for both single-ended and differential input interfaces of varying
input spans. The sample-and-hold amplifier (SHA) is equally
suited for both multiplexed systems that switch full-scale voltage
levels in successive channels as well as sampling single-channel
inputs at frequencies up to and beyond the Nyquist rate. Also,
the AD9241 performs well in communication systems employ-
ing Direct-IF Down Conversion since the SHA in the differen-
tial input mode can achieve excellent dynamic performance well
beyond its specified Nyquist frequency of 0.625 MHz.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an over-
flow condition which can be used with the most significant bit
to determine low or high overflow.
FEATURES
Monolithic 14-Bit, 1.25 MSPS A/D Converter
Low Power Dissipation: 60 mW
Single +5 V Supply
Integral Nonlinearity Error: 2.5 LSB
Differential Nonlinearity Error: 0.6 LSB
Input Referred Noise: 0.36 LSB
Complete: On-Chip Sample-and-Hold Amplifier and
Signal-to-Noise and Distortion Ratio: 78.0 dB
Spurious-Free Dynamic Range: 88.0 dB
Out-of-Range Indicator
Straight Binary Output Data
44-Pin MQFP
Voltage Reference
PRODUCT HIGHLIGHTS
The AD9241 offers a complete single-chip sampling 14-bit,
analog-to-digital conversion function in a 44-pin Metric Quad
Flatpack.
Low Power and Single Supply
The AD9241 consumes only 60 mW on a single +5 V power
supply.
Excellent DC Performance Over Temperature
The AD9241 provides no missing codes, and excellent tempera-
ture drift performance over the full operating temperature range.
Excellent AC Performance and Low Noise
The AD9241 provides nearly 13 ENOB performance and has an
input referred noise of 0.36 LSB rms.
Flexible Analog Input Range
The versatile onboard sample-and-hold (SHA) can be configured
for either single-ended or differential inputs of varying input spans.
Flexible Digital Outputs
The digital outputs can be configured to interface with +3 V and
+5 V CMOS logic families.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
SENSE
CAPT
CAPB
VREF
VINB
VINA
CML
Complete 14-Bit, 1.25 MSPS
SHA
SELECT
MODE
Monolithic A/D Converter
FUNCTIONAL BLOCK DIAGRAM
A/D
GAIN = 16
MDAC1
REFCOM
5
5
World Wide Web Site: http://www.analog.com
CLK
1V
DIGITAL CORRECTION LOGIC
AD9241
A/D
OUTPUT BUFFERS
GAIN = 8
MDAC2
4
AVSS
AVDD
4
14
© Analog Devices, Inc., 1997
DVDD
DVSS
A/D
GAIN = 8
MDAC3
4
AD9241
4
DRVDD
DRVSS
A/D
4
OTR
BIT 1
(MSB)
BIT 14
(LSB)

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AD9241 Summary of contents

Page 1

... The AD9241 offers a complete single-chip sampling 14-bit, analog-to-digital conversion function in a 44-pin Metric Quad Flatpack. Low Power and Single Supply The AD9241 consumes only single +5 V power supply. Excellent DC Performance Over Temperature The AD9241 provides no missing codes, and excellent tempera- ture drift performance over the full operating temperature range ...

Page 2

... DVDD DRVDD Supply Current IAVDD IDRVDD IDVDD POWER CONSUMPTION NOTES 1 VREF = Including internal reference. 3 Excluding internal reference. 4 Load regulation with 1 mA load current (in addition to that required by the AD9241). Specification subject to change without notice. SAMPLE unless otherwise noted) MAX AD9241 14 1.25 0.9 0.36 2.5 0.6 1.0 2.5 0.7 14 ...

Page 3

... AD9241 +3.5 +1 +4.5 +2.4 +0.4 +0.1 5 +2.4 +0.7 AD9241 Units dB typ dB min dB typ Bits typ Bits min Bits typ dB typ dB min dB typ dB typ dB max dB typ dB typ dB typ MHz typ MHz typ ns typ ps rms typ ns typ ns typ Units V min V max ...

Page 4

... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9241 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

Page 5

... The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It may be reported in dBc (i.e., degrades as signal level is lowered dBFS (always related back to converter full scale). –5– AD9241 ...

Page 6

... AD9241 Typical Differential AC Characterization Curves/Plots 80 –0.5dBFS 75 70 –6.0dBFS 65 60 –20dBFS 0.01 1.0 10.0 0.1 INPUT FREQUENCY – MHz Figure 2. SINAD vs. Input Frequency (Input Span = 2 –0.5dBFS 70 65 –6.0dBFS 60 55 –20.0dBFS 0.01 0.1 1.0 10.0 INPUT FREQUENCY – MHz Figure 5. SINAD vs. Input Frequency (Input Span = ...

Page 7

... INPUT FREQUENCY – MHz Figure 18. THD vs. Input Frequency (Input Span = 2 –7– AD9241 = 1.25 MSPS +25 C, SAMPLE A 12,901,627 1,137,700 1,146,291 N–1 N N+1 CODE Figure 13. “Grounded-Input” Histogram (Input Span = ...

Page 8

... The output drivers can be con- figured to interface with + +3.3 V logic families. The AD9241 uses both edges of the clock in its internal timing circuitry (see Figure 1 and specification page for exact timing requirements). The A/D samples the analog input on the rising edge of the clock input ...

Page 9

... The input SHA of the AD9241 is optimized to meet the perfor- mance requirements for some of the most demanding commu- nication, imaging and data acquisition applications, while maintaining low power dissipation. Figure graph of the full-power bandwidth of the AD9241, typically 40 MHz. Note that the small signal bandwidth is the same as the full-power bandwidth ...

Page 10

... VINA and/or VINB) and analog ground. Since this additional shunt capacitance combines with the equivalent input capaci- to tance of the AD9241, a lower series resistance can be selected to establish the filter’s cutoff frequency while not degrading the distortion performance of the device. The shunt capacitance ...

Page 11

... AVDD. Disabling the reference amplifier allows the VREF pin to be driven by an external voltage reference. The actual reference voltages used by the internal circuitry of the AD9241 appear on the CAPT and CAPB pins. For proper operation when using the internal or an external reference necessary to add a capacitor network to decouple these pins. ...

Page 12

... VSWR. The centertap of the transformer provides a convenient means of level-shifting the input signal to a desired common-mode voltage. Optimum performance can be realized when the centertap is tied to CML of the AD9241 which is the common-mode bias level of the internal SHA. 50 0.1µF ...

Page 13

... AD9241 differentially. Since the signal swing require- ments of each input is reduced by a factor of two in the differential mode, the AD9241 can be configured for input span system. This allows various high performance op amps specified for +5 V and 5 V operation to be configured in various differential driver topologies ...

Page 14

... AD9241 If the application requires the largest single-ended input range (i.e the AD9241, the op amp will require larger supplies to drive it. Various high speed amplifiers in the Op Amp Selection Guide of this data sheet can be selected to accommodate a wide range of supply options. Once again, clamp- ing the output of the amplifier should be considered for these applications ...

Page 15

... Figure 27. USING THE INTERNAL REFERENCE Single-Ended Input with Figure 36 shows how to connect the AD9241 for input range via pin strapping the SENSE pin. An inter- mediate input range VREF can be established using the resistor programmable configuration in Figure 38 and con- necting VREF to VINB ...

Page 16

... set at midsupply by connecting the transformers center CM tap to CML of the AD9241. VREF can be configured for 2 connecting SENSE to either VREF or REFCOM respectively. Note that the valid input range for each of the differential inputs is one half of the single-ended input and thus becomes V – ...

Page 17

... REF191, a 2.048 external reference, was selected, the valid input range extends from 4.096 V. In this case, 1 LSB of the AD9241 corresponds to 0.250 mV essential that a minimum capacitor in parallel with a 0.1 F low induc- tance ceramic capacitor decouple the reference output to ground. ...

Page 18

... Most of the power dissipated by the AD9241 is from the analog power supply. However, lower clock speeds will slightly reduce digital current. Figure 44 shows the relationship between power and clock rate ...

Page 19

... Figure 46. Analog Supply Decoupling REV. 0 The CML is an internal analog bias point used internally by the AD9241. This pin must be decoupled with at least a 0.1 F capacitor as shown in Figure 47. The dc level of CML is ap- proximately AVDD/2. This voltage should be buffered used for any external biasing. ...

Page 20

... AD9241 AVSS1 AVSS2 AVDD1 AVDD2 DVDD DRVDD DVSS DRVSS Figure 49. Evaluation Board Schematic –20– SJ5 SJ4 SJ3 SJ2 SJ1 JG1 REV. 0 ...

Page 21

... Figure 50. Evaluation Board Component Side Layout (Not to Scale) Figure 51. Evaluation Board Solder Side Layout (Not to Scale) REV. 0 –21– AD9241 ...

Page 22

... AD9241 Figure 52. Evaluation Board Ground Plane Layout (Not to Scale) Figure 53. Evaluation Board Power Plane Layout (Not to Scale) –22– REV. 0 ...

Page 23

... OUTLINE DIMENSIONS Dimensions shown in mm and (inches). 44-Pin Metric Quad Flatpack (MQFP) (S-44) 13.45 (0.529) 12.95 (0.510) 2.45 (0.096) 10.1 (0.398) MAX 9.90 (0.390 MIN 1 SEATING PLANE TOP VIEW (PINS DOWN) 11 0.25 (0.01) 12 MIN 0.8 (0.031) 0.45 (0.018) BSC 2.1 (0.083) 0.3 (0.012) 1.95 (0.077) –23– AD9241 34 33 8.45 (0.333) 8.3 (0.327 ...

Page 24

–24– ...

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