AD976A Analog Devices, AD976A Datasheet - Page 13

• Manufacturer Part Number: AD976A
• Description: 16-Bit, 200 kSPS, Parallel I/O A/D Converter
• Manufacturer: Analog Devices

Specifications of AD976A

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 200kSPS
• Interface: Par
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip 10V
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

REV. C
DC CODE UNCERTAINTY
Ideally, a fixed dc input should result in the same output code
for repetitive conversions; however, as a consequence of un-
avoidable circuit noise within the wideband circuits of the ADC,
a range of output codes may occur for a given input voltage.
Thus, when a dc signal is applied to the AD976/AD976A input,
and 10,000 conversions are recorded, the result will be a distri-
bution of codes as shown in Figure 19. This histogram shows a
bell-shaped curve consistent with the Gaussian nature of ther-
mal noise. The histogram is approximately seven codes wide.
The standard deviation of this Gaussian distribution results in a
code transition noise of 1 LSB rms.
Figure 19. Histogram of 10,000 Conversions of a DC Input
Figure 17. Typical Position DNL Distribution (1516 Units)
4000
3500
3000
2500
2000
1500
1000
250
200
150
100
500
50
0
0
–3
–2
POSITIVE DNL DISTRIBUTION – LSB
–1
0
1
2
3
4
–13–
MICROPROCESSOR INTERFACING
The AD976/AD976A is ideally suited for traditional dc mea-
surement applications supporting a microprocessor and ac signal
processing applications interfacing to a digital signal processor.
The AD976/AD976A is designed to interface with a 16-bit data
bus and provides all output data bits in a single read cycle. A
variety of external buffers can be used with the AD976/AD976A
to prevent bus noise from coupling into the ADC. The following
sections illustrate the use of the AD976/AD976A with the
MC68000 and 8051 microcontrollers and the TMS320C25 and
ADSP-2111 signal processors.
MC68000 Interface
Figure 20 shows a general interface diagram for the MC68000
16-bit microprocessor to the AD976/AD976A. In Figure 20,
conversion is initiated by bringing CSA low (i.e., writing to the
appropriate address). This allows the processor to maintain
control over the complete conversion process.
Figure 18. Typical Negative DNL Distribution (1516 Units)
68000
Figure 20. AD976/AD976A to 68000 Interface
140
120
100
40
80
60
20
0
R/W
D15
A15
AS
A0
D0
*ADDITIONAL PINS OMITTED FOR CLARITY
NEGATIVE DNL DISTRIBUTION – LSB
ADDRESS BUS
DATA BUS
EN
DECODE
ADDR
Q15
Q0
OE
74HC374
AD976/AD976A
CLK
D15
D0
BUS
DB15
R/C
BUSY
DB0
AD976A
AD976/