AD7722 Analog Devices, AD7722 Datasheet
AD7722
Specifications of AD7722
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AD7722 Summary of contents
Page 1
... The AD7722 is available in a 44-lead MQFP package and is specified over the industrial temperature range of –40°C to +85°C. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...
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... AD7722–SPECIFICATIONS UNI = Logic Low or High 12.5 MHz; f CLKIN Parameter 2 DYNAMIC SPECIFICATIONS Bipolar Mode, UNI = V INH 3 Signal-to-(Noise + Distortion) 3 Total Harmonic Distortion Spurious-Free Dynamic Range Unipolar Mode, UNI = V INL 3 Signal-to-(Noise + Distortion) 3 Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion AC CMRR Digital Filter Response ...
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... Applies after calibration at temperature of interest. 5 Gain error excludes reference error. The ADC gain is calibrated w.r.t. the voltage on the REF2 pin. Specifications subject to change without notice. REV 200 µA OUT | = 1.6 mA OUT and –3– AD7722 A Version Min Typ Max 2.0 0.8 4.0 0.4 ± 4.0 0.4 4.75 5.25 4.75 5 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7722 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... CLK CLK – 10 CLK 50 (8192 + 64) 8192 × 8192 + 2 × 512) (4 × 8192 + 3 × 512) (3 × 8192 + 2 × 512 + 64) (4 × 8192 + 3 × 512 + 64) AD7722 , MAX Unit MHz µ CLK CLK CLK ns ns ...
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... AD7722 CLKIN SCO (CFMT = 0) FSO (SFMT = 0) SCO Figure 2a. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE) CLKIN SCO (CFMT = 0) FSO (SFMT = 1) SCO Figure 2b. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE) 2.3V CLKIN FSI SCO Figure 3. Serial Mode Timing for Clock Input, Frame Sync Input, and Serial Clock Output ...
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... VALID DATA Figure 6. Parallel Mode Read Timing t 30 MAX UNI = UNI = 8192 8192 CLK CLK t t 512 512 CLK CLK –7– 8192 8192 CLK CLK t 512 CLK t 38 AD7722 ...
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... MΩ resistor should be connected between the CLKIN and XTAL pins with two capacitors connected from each pin to ground. Alternatively, the CLKIN pin can be driven with an external CMOS compatible clock. The AD7722 is specified with a clock input frequency of 12.5 MHz. ...
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... PIN 1 2 IDENTIFIER 3 4 DVAL/RD 5 AD7722 DGND 6 TOP VIEW (Not to Scale) UNI 7 P/S 8 AGND 9 AGND1 10 CLKIN –9– AD7722 33 DGND/DB13 DGND/DB14 32 31 DGND/DB15 SYNC DGND 28 CAL 27 AGND 26 AGND 25 24 REF2 ...
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... SDO can be three-state after a serial data transmission by connecting DOE to FSO. This input is useful when two AD7722s are connected to the same serial data bus. When using a single ADC, to ensure SDO is active, connect DOE to DGND so that it equals the logic level of TSI. ...
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... The frequency above which the AD7722’s frequency response will be within its stop-band attenuation. ) Stop-Band Attenuation The AD7722’s frequency response will not have less than of attenuation in the stated frequency band. 1 Integral Nonlinearity , V , ...
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... AD7722–Typical Performance Characteristics ( 5 CLKIN = 12.5 MHz, AIN = 20 kHz, Bipolar Mode 110 100 90 SFDR 80 S/ (N+ –40 –30 –20 –10 0 INPUT LEVEL (dB) TPC 1. S/(N+D) and SFDR vs. Analog Input Level –85 –90 SNR V (+) = V (–) = 1.25V p – 2.5V CM THD – ...
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... S/(N+D) = 87.8dB –40 SFDR = –94.3dB THD = –93.8dB –60 2ND = –94.3dB 3RD = –108.5dB –80 4TH = –105.7dB –100 –120 –140 –154 –13– AD7722 2.5 5.0 7.5 10.0 12.5 CLKIN FREQUENCY (MHz) AIN = 90kHz XTAL = 12.288MHz SNR = 88.1dB S/(N+D) = 88.1dB SFDR = –103.7dB 20 ...
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... CLKIN CLKIN Out-of-band signals coincident with any of the filter images are aliased into the pass band. However, due to the AD7722’s high oversampling ratio, these bands occupy only a small fraction of the spectrum, and most broadband noise is filtered. This means that the antialias filtering requirements in front of the AD7722 are considerably reduced versus a conventional converter with no on-chip filtering ...
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... This nonlinear response, which can cause excessive ringing, can lead to distortion. To remedy the situation, a low-pass RC filter can be connected between the amplifier and the input to the AD7722 as shown in Figure 14. The external capacitor at each V –1LSB REF2 input aids in supplying the current spikes created during the (+) – ...
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... Even though the voltage on the input sampling capacitors may not have enough time to settle to the accuracy indicated by the resolu- tion of the AD7722, as long as the sampling capacitor charging follows the exponential curve of RC circuits, only the gain accuracy suffers if the input capacitor is switched away too early. ...
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... V. For single-ended applications, best THD performance is obtained with V (–) set to 1.25 V rather than 2.5 V. The IN input to the AD7722 can also be driven differentially with a complementary input, as shown in Figure 20. In this case, the input common-mode voltage is set to 2.5 V. The 2.5 V p-p full-scale differential input is obtained with a 1 ...
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... AD7722 Varying the Master Clock Although the AD7722 is specified with a master clock of 12.5 MHz, the AD7722 operates with clock frequencies MHz and as low as 300 kHz. The input sample rate, output word rate, and frequency response of the digital filter are directly proportional to the master clock frequency ...
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... When using the AD7722, place a buffer/latch adjacent to the converter to isolate the converter’s data lines from any noise that may be on the data bus. Even though the AD7722 has three-state outputs, use of an isolation latch represents good design practice. This arrangement will inject a small amount of digital noise on the AD7722 ground plane ...
Page 20
... MSB is available and returns high after 16 SCO cycles. The frame sync input (FSI) can be used if the AD7722 conver- sion process must be synchronized to an external source. FSI is an optional signal; if FSI is grounded or tied high frame syncs are internally generated ...
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... To interface the AD7722 to other DSPs, the master clock frequency of the AD7722 can be reduced so that the SCO frequency equals the maximum allowable frequency of the serial clock input to the DSP. When the AD7722 is operated with a lower CLKIN frequency (< 10 MHz), DSPs, such as the TMS320C20/C25 and DSP56000/1, can be used. ...
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... The analog ground plane should be allowed to run under the AD7722 to shield it from noise coupling. The power supply lines to the AD7722 should use as large a trace as possible (preferably a plane) to provide a low impedance path and reduce the effects of glitches on the power supply line. ...
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... SEATING COPLANARITY REV. B OUTLINE DIMENSIONS 44-Lead Metric Quad Flat Package [MQFP] (S-44B) Dimensions shown in millimeters 14.15 1.03 13.90 SQ 0.88 2.45 13.65 MAX 0. 0.8 34 PLANE TOP VIEW (PINS DOWN) 0.10 PIN 2.10 2.00 0.80 0.25 MAX 1.96 BSC COMPLIANT TO JEDEC STANDARDS MS-022-AA-1 –23– AD7722 23 22 10.20 10. 0.45 0.30 ...
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... AD7722 Revision History Location 10/03—Data Sheet changed from REV REV. B. Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Replaced Figures 7 and Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Text added to 2-Channel Multiplexed Operation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Replaced Figure Changes to text in 2-Channel Multiplexed Operation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Changes to Figure Change to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5/03— ...