AD5790 Analog Devices, AD5790 Datasheet - Page 22

• Manufacturer Part Number: AD5790
• Manufacturer: Analog Devices

Specifications of AD5790

• Resolution (bits): 20bit
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser

AD5790
Control Register
The control register controls the mode of operation of the
AD5790.
Table 10. Control Register
MSB
DB23
R/ W
R/ W
Table 11. Control Register Functions
Bit Name
Reserved
RBUF
OPGND
DACTRI
BIN/2sC
SDODIS
R/W
Table 12. Clearcode Register
MSB
DB23
R/W
R/W
DB22
0
Register address
DB21
1
Description
These bits are reserved and should be programmed to zero.
Output amplifier configuration control.
0: the internal amplifier, A1, is powered up and Resistors R
allows an external amplifier to be connected in a gain of two configuration. See the
details.
1: (default) the internal amplifier, A1, is powered down and Resistors R
so that the resistance between the R
pins to be used for input bias current compensation for an external unity-gain amplifier. See the
for further details.
Output ground clamp control.
0: the DAC output clamp to ground is removed and the DAC is placed in normal mode.
1: (default) the DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate mode.
Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated.
Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit.
DAC tristate control.
0: the DAC is in normal operating mode.
1: (default) DAC is in tristate mode.
DAC register coding selection.
0: (default) the DAC register uses twos complement coding.
1: the DAC register uses offset binary coding.
SDO pin enable/disable control.
0: (default) the SDO pin is enabled.
1: the SDO pin is disabled (tristate).
Read/write select bit.
0:
1:
AD5790
AD5790
DB22
0
DB20
0
is addressed for a write operation.
is addressed for a read operation.
DB19 to DB11
Reserved
DB21
1
Register address
DB10
Reserved
FB
and INV pins is 3.4 kΩ, equal to the resistance of the DAC. This allows the R
DB9
Rev. B | Page 22 of 28
DB20
1
DB8
0000
DB7
FB
Clearcode Register
The clearcode register sets the value to which the DAC output is
set when the CLR pin or CLR bit in the software control register
is asserted. The output value depends on the DAC coding that is
being used, either binary or twos complement. The default
register value is 0.
and R1 are connected in series, as shown in Figure 54. This
Control register data
DB6
DB19 to DB0
Clearcode register data
20 bits of data
FB
DB5
SDODIS
and R1 are connected in parallel, as shown in Figure 53,
DB4
BIN/2sC
AD5790
DB3
DACTRI
Features section for further
AD5790
DB2
OPGND
Features section
Data Sheet
DB1
RBUF
FB
and INV
DB0
Reserved
LSB
LSB