AD9146 Analog Devices, AD9146 Datasheet - Page 20

• Manufacturer Part Number: AD9146
• Description: Dual, 16-Bit, 1230 MSPS, TxDAC+® Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9146

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Byte,LVDS,Nibble

AD9146
Table 11. Device Configuration Register Descriptions
Register
Name
Comm
Power
Control
Tx Enable
Control
Address
(Hex)
0x00
0x01
0x02
Bits
7
6
5
7
6
5
4
3
2
6
5
4
3
2
1
0
Name
SDIO
LSB_FIRST
Reset
Power down I DAC
Power down Q DAC
Power down data
receiver
Power down auxiliary
ADC
Power down auxiliary
DACs and reference
Power down clocks
Extended delay length
Enable extended delay
Power down voltage
reference
Power down PLL
Power down DACs
Power down FIFO
Power down filters
Rev. A | Page 20 of 56
from when the TXENABLE pin is brought high.
0 = disable the extended delay option. Delays the outputs
by 1 to 2 DAC/64 clock edges.
1 = enable the extended delay option. Delays the outputs
based on the setting of Bit 6.
Description
SDIO pin operation. To enable data readback, set this bit to 1.
0 = SDIO operates as an input only.
1 = SDIO operates as a bidirectional input/output.
Serial port communication, LSB or MSB first.
0 = MSB first.
1 = LSB first.
The device is placed in reset when this bit is written high
and remains in reset until the bit is written low.
1 = power down I DAC.
1 = power down Q DAC.
1 = power down the input data receiver.
1 = power down the auxiliary ADC for temperature sensor.
1 = power down the auxiliary DACs and the voltage reference.
1 = power down the clocks.
Time delay from when the TXENABLE pin is brought high to
when the DAC begins transmitting data. See the Tx Enable
section for more information.
0 = delay the outputs by 12 to 13 DAC/64 clock edges.
1 = delay the outputs by 19 to 20 DAC/64 clock edges.
The transmit delay, regardless of whether the extended delay
option is selected, has an inherent fixed delay of 10 DAC clock
cycles. When the extended delay is disabled, there is a mini-
mum delay time in the outputs of 1 to 2 DAC/64 clock edges
0 = no power-down of the internal voltage reference.
1 = power down the internal voltage reference when the
TXENABLE pin is held low.
0 = no power-down of the on-chip PLL.
1 = power down the on-chip PLL when the TXENABLE pin is
held low.
0 = no power-down of the DAC cores.
1 = power down the DAC cores when the TXENABLE pin is
held low.
0 = no power-down of the FIFO.
1 = power down the FIFO when the TXENABLE pin is held
low.
0 = no power-down of the interpolation filters.
1 = power down the interpolation filters when the
TXENABLE pin is held low.
Data Sheet
Default
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0