AD5542A Analog Devices, AD5542A Datasheet - Page 6

• Manufacturer Part Number: AD5542A
• Manufacturer: Analog Devices

Specifications of AD5542A

• Resolution (bits): 16bit
• Dac Update Rate: n/a
• Dac Settling Time: 1µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Unbuffered Vout
• Dac Input Format: Ser,SPI

AD5512A/AD5542A
TIMING CHARACTERISTICS
V
Table 5.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
SCLK
1
2
3
4
5
6
7
8
9
9
10
11
12
13
Guaranteed by design and characterization, not production tested.
All input signals are specified with t
−40°C < T
−40°C < T
DD
= 5 V, 2.5 V ≤ V
A
A
< +105°C.
< +125°C.
1, 2
LDAC
SCLK
NOTES
CLR
1. FOR AD5542A = DB15.
2. FOR AD5512A = DB11.
DIN
Limit 1.8 ≤ V
14
70
35
35
5
5
5
10
35
5
5
20
10
15
15
CS
REF
≤ V
DD
t
12
, V
LOGIC
R
t
= t
6
INH
F
≤ 2.7 V
= 1 ns/V and timed from a voltage level of (V
DB15
t
DB11
t
4
= 90% of V
8
t
9
1
2
3
Limit 2.7 V ≤ V
50
20
10
10
5
5
5
5
10
4
5
20
10
15
15
LOGIC
, V
INL
t
2
= 10% of V
Figure 3. Timing Diagram
LOGIC
Rev. A | Page 6 of 24
t
13
≤ 5.5 V
t
1
t
3
LOGIC
4
INL
, AGND = DGND = 0 V, unless otherwise noted.
+ V
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns
INH
)/2.
t
7
t
t
5
11
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time (V
Data hold time (V
LDAC pulsewidth
CS high to LDAC low setup
CS high time between active periods
CLR pulsewidth
t
10
INH
INH
= 90% of V
= 3 V, V
INL
= 0 V)
DD
, V
INL
= 10% of V
DD
)