AD5629R Analog Devices, AD5629R Datasheet - Page 22

• Manufacturer Part Number: AD5629R
• Manufacturer: Analog Devices

Specifications of AD5629R

• Resolution (bits): 12bit
• Dac Update Rate: 166kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

AD5629R/AD5669R
Table 8. Command Definitions
C3
0
0
0
0
0
0
0
0
1
1
1
–
1
Table 9. Address Commands
A3
0
0
0
0
0
0
0
0
1
(CONTINUED)
(CONTINUED)
Command
C2
0
0
0
0
1
1
1
1
0
0
0
–
1
SCL
SDA
A2
0
0
0
0
1
1
1
1
1
Address (n)
START BY
MASTER
C1
0
0
1
1
0
0
1
1
0
0
1
–
1
SDA
SCL
A1
0
0
1
1
0
0
1
1
1
C0
0
1
0
1
0
1
0
1
0
1
0
–
1
1
1
Description
Write to Input Register n
Update DAC Register n
Write to Input Register n; update all
(software LDAC)
Write to and update DAC Channel n
Power down/power up DAC
Load clear code register
Load LDAC register
Reset (power-on reset)
Set up internal REF register
Enable multiple byte mode
Reserved
Reserved
Reserved
DB15 DB14 DB13 DB12
1
A0
0
1
0
1
0
1
0
1
1
0
1
Selected DAC Channel
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
All DACs
SLAVE ADDRESS
FRAME 1
0
MOST SIGNIFICANT
1
DATA BYTE
FRAME 3
DB11 DB10
A1
A0
AD5629R/AD5669R
R/W
DB9
Figure 51. I
ACK. BY
Rev. A | Page 22 of 28
9
DB8
ACK. BY
MASTER
2
C Read Operation
1
DB23
9
1
DB22 DB21 DB20 DB19 DB18 DB17
DB7
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. Data is loaded into the
device as a 24-bit word under the control of a serial clock input,
SCL. The input register contents for this operation is shown in
Figure 52 and Figure 53. The eight MSBs make up the command
byte. DB23 to DB20 are the command bits, C3, C2, C1, and C0,
that control the mode of operation of the device (see Table 9 for
details). The last four bits of the first byte are the address bits,
A3, A2, A1, and A0, (see Table 9 for details). The rest of the bits
are the 16-/12-bit data-word.
The AD5669R data-word comprises the 16-bit input code (see
Figure 52) while the AD5629R data word is comprised of 12-
bits followed by four don’t cares (see Figure 53).
MULTIPLE BYTE OPERATION
Multiple byte operation is supported on the AD5629R/ AD5669R.
Command 1001 is reserved for multiple byte operation (see
Table 8) A 2-byte operation is useful for applications that
require fast DAC updating and do not need to change the
command byte. The S bit (DB22) in the command register
can be set to 1 for the 2-byte mode of operation. For standard
3-byte and 4-byte operation, the S bit (DB22) in the command
byte should be set to 0.
DB6
DB5
COMMAND BYTE
FRAME 2
LEAST SIGNIFICANT
DB4
DATA BYTE
FRAME 4
DB3
DB2
DB16
DB1
MASTER
ACK. BY
9
DB0
NO ACK.
9
STOP BY
MASTER