AD9122 Analog Devices, AD9122 Datasheet - Page 58

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9122
SED EXAMPLE
Normal Operation
The following example illustrates the SED configuration for
continuously monitoring the input data and assertion of the
IRQ pin when a single error is detected.
1.
2.
3.
Load the following comparison values. (Comparison values
can be chosen arbitrarily; however, choosing values that
require frequent bit toggling provides the most robust test.)
Register 0x68: I0[7:0]
Register 0x69: I0[15:8]
Register 0x6A: Q0[7:0]
Register 0x6B: Q0[15:8]
Register 0x6C: I1[7:0]
Register 0x6D: I1[15:8]
Register 0x6E: Q1[7:0]
Register 0x6F: Q1[15:8]
Enable the SED error detect flag to assert the IRQ pin.
(Set Register 0x05 to 0x04.)
Begin transmitting the input data pattern.
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4.
5.
If IRQ is asserted, read Register 0x67 and Register 0x70 through
Register 0x73 to verify that a SED error was detected and to deter-
mine which input bits were in error. The bits in Register 0x70
through Register 0x73 are latched; therefore, the bits indicate
any errors that occurred on those bits throughout the test (not
only the errors that caused the error detected flag to be set).
Note that the FRAME signal is not required during normal
operation when the device is configured for word mode.
Enabling the alignment of the I0 sample as described in the
SED Operation section requires the use of the FRAME signal.
The timing diagrams for byte and nibble modes are the same
as during normal operation and are shown in Figure 44 and
Figure 45, respectively.
Write to Register 0x67 to enable the SED.
(Set Register 0x67 to 0x80.)
Clear the SED errors in Register 0x67 and Register 0x07.
When the SED is first turned on, the FRAME signal may
be detected immediately; therefore, the SED failure bit may
be asserted due to the unknown initial FRAME status. For
this reason, the SED compare fail status bit must be cleared
at least once immediately after enabling the SED.