AD5066 Analog Devices, AD5066 Datasheet - Page 5

• Manufacturer Part Number: AD5066
• Description: Fully Accurate, 16-Bit, UnBuffered VOUT Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP
• Manufacturer: Analog Devices

Specifications of AD5066

• Resolution (bits): 16bit
• Dac Settling Time: 12µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Unbuffered Vout
• Dac Input Format: Ser,SPI

TIMING CHARACTERISTICS
All input signals are specified with t
5.5 V, all specifications T
Table 4.
Parameter
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Set-Up Time
Data Set-Up Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SYNC Rising Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SCLK Falling Edge to LDAC Rising Edge
CLR Pulse Width Low
SCLK Falling Edge to LDAC Falling Edge
CLR Pulse Activation Time
1
Maximum SCLK frequency is 50 MHz. Guaranteed by design and characterization; not production tested.
Single Channel Update
All Channel Update
1
L D A C
L D A C
1
2
S Y N C
A S Y N C H R O N O U S L D A C U P D A T E M O D E .
S Y N C H R O N O U S L D A C U P D A T E M O D E .
S C L K
V
C L R
O U T
D IN
1
2
MIN
to T
MAX
t
8
, unless otherwise noted. See Figure 2.
R
= t
D B 31
F
= 1 ns/V (10% to 90% of V
t
12
t
4
t
5
t
1 4
t
6
t
3
Figure 2. Serial Write Operation
t
Rev. A | Page 5 of 24
1
t
2
DD
D B 0
t
t
) and timed from a voltage level of (V
7
13
t
9
t
10
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
14
t
11
Min
20
10
10
17
5
5
5
3
8
17
20
20
10
10
10.6
Typ
IL
+ V
IH
)/2, V
Max
30
DD
= 2.7 V to
AD5066
Unit
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
µs