AD5722R Analog Devices, AD5722R Datasheet - Page 6

• Manufacturer Part Number: AD5722R
• Description: Complete, Dual, 12-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DAC
• Manufacturer: Analog Devices

Specifications of AD5722R

• Resolution (bits): 12bit
• Dac Update Rate: 1.07MSPS
• Dac Settling Time: 7.5µs
• Max Pos Supply (v): +16.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5722R/AD5732R/AD5752R
TIMING CHARACTERISTICS
AV
C
Table 4.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Guaranteed by characterization; not production tested.
All input signals are specified with t
See Figure 2, Figure 3, and Figure 4.
Daisy-chain and readback mode.
C
LOAD
L SDO
4
4
DD
= capacitive load on SDO output.
= 200 pF; all specifications T
= 4.5 V to 16.5 V; AV
1, 2, 3
Limit at t
33
13
13
13
13
100
7
2
20
130
20
10
20
2.5
13
40
200
SS
= −4.5 V to −16.5 V, or AV
R
= t
MIN
F
MIN
= 5 ns (10% to 90% of DV
, t
to T
MAX
MAX
, unless otherwise noted.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs typ
ns min
μs max
ns min
ns max
ns min
CC
SS
) and timed from a voltage level of 1.2 V.
= 0 V; GND = 0 V; REFIN = 2.5 V external; DV
Rev. D | Page 6 of 32
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (write mode)
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
DAC output settling time
CLR pulse width low
CLR pulse activation time
SYNC rising edge to SCLK rising edge
SCLK rising edge to SDO valid (C
Minimum SYNC high time (readback/daisy-chain mode)
L SDO
5
= 15 pF)
CC
= 2.7 V to 5.5 V; R
LOAD
= 2 kΩ;