AD5722 Analog Devices, AD5722 Datasheet - Page 5

• Manufacturer Part Number: AD5722
• Description: Complete, Dual, 12-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DAC
• Manufacturer: Analog Devices

Specifications of AD5722

• Resolution (bits): 12bit
• Dac Update Rate: 1MSPS
• Dac Settling Time: 10µs
• Max Pos Supply (v): +16.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AC PERFORMANCE CHARACTERISTICS
AV
C
Table 2.
Parameter
DYNAMIC PERFORMANCE
1
2
TIMING CHARACTERISTICS
AV
200 pF; all specifications t
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
For specified performance, the maximum headroom requirement is 0.9 V.
Guaranteed by design and characterization; not production tested.
Guaranteed by characterization; not production tested.
All input signals are specified with t
See Figure 2, Figure 3, and Figure 4.
Daisy-chain and readback mode.
C
LOAD
4
L SDO
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Digital Crosstalk
DAC-to-DAC Crosstalk
Digital Feedthrough
Output Noise
Output Noise Spectral Density
4
DD
DD
0.1 Hz to 10 Hz Bandwidth
100 kHz Bandwidth
= capacitive load on SDO output.
= 4.5 V
= 4.5 V to 16.5 V; AV
= 200 pF; all specifications T
2
1, 2, 3
1
to 16.5 V; AV
Limit at t
33
13
13
13
13
100
7
2
20
130
20
10
20
2.5
13
40
200
MIN
SS
SS
to t
= −4.5 V to −16.5 V, or AV
= −4.5 V to −16.5 V, or AV
R
= t
MAX
MIN
F
= 5 ns (10% to 90% of DV
MIN
, unless otherwise noted.
, t
MAX
to T
MAX
, unless otherwise noted.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs max
ns min
μs max
ns min
ns max
ns min
Min
CC
SS
) and timed from a voltage level of 1.2 V.
SS
= 0 V; GND = 0 V; REFIN = 2.5 V; DV
= 0 V; GND = 0 V; REFIN = 2.5 V; DV
Rev. D | Page 5 of 32
10
0.6
Typ
7.5
3.5
13
35
10
10
15
80
320
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (write mode)
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
DAC output settling time
CLR pulse width low
CLR pulse activation time
SYNC rising edge to SCLK falling edge
SCLK rising edge to SDO valid (C
Minimum SYNC high time (readback/daisy-chain mode)
Max
12
8.5
5
Unit
μs
μs
μs
V/μs
nV-sec
mV
nV-sec
nV-sec
nV-sec
μV p-p
μV rms
nV/√Hz
Test Conditions/Comments
20 V step to ±0.03% FSR
512 LSB step settling (16-bit resolution)
Measured at 10 kHz, 0x8000 DAC code
10 V step to ±0.03% FSR
0x8000 DAC code
L SDO
CC
CC
AD5722/AD5732/AD5752
= 2.7 V to 5.5 V; R
= 2.7 V to 5.5 V; R
5
= 15 pF)
LOAD
LOAD
= 2 kΩ; C
= 2 kΩ;
LOAD
=