AD5734 Analog Devices, AD5734 Datasheet
AD5734
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AD5734 Summary of contents
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... The parts offer guaranteed monotonicity, integral nonlinearity (INL) of ±16 LSB maximum, low noise, and 10 μs maximum settling time. The AD5724/AD5734/AD5754 use a serial interface that operates at clock rates MHz and are compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs ...
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... Load DAC ( LDAC )..................................................................... 20 Asynchronous Clear ( CLR )....................................................... 20 Configuring the AD5724/AD5734/AD5754 .......................... 20 REVISION HISTORY 7/11—Rev Rev. D Changes to Table 3: t7, t8, t10 Limits......................................................5 3/11—Rev Rev. C Changes to Configuring the AD5724/AD5734/AD5754 Section.............................................................................................. 20 8/10—Rev Rev. B Changes to Table 27........................................................................ 26 4/10—Rev Rev. A Changes to Junction Temperature, T max Parameter, Table Changes to Exposed Pad Description, Table 5 ...
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... V ±4 ppm FSR/° kΩ 4000 pF 0.5 Ω Rev Page AD5724/AD5734/AD5754 = 2 5 kΩ; CC LOAD Test Conditions/Comments Outputs unloaded All models, all versions, guaranteed monotonic T = 25°C, error at other temperatures obtained A using bipolar zero error 25°C, error at other temperatures ...
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... Power Dissipation Power-Down Currents For specified performance, maximum headroom requirement is 0 INL is measured from Code 512, Code 128, and Code 32 for the AD5754, the AD5734, and the AD5724, respectively. 3 Guaranteed by characterization; not production tested. Min Typ Max Unit 2 V 0.8 V ± ...
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... SYNC rising edge to SCLK rising edge ns max SCLK rising edge to SDO valid (C ns min Minimum SYNC high time (readback/daisy-chain mode) ) and timed from a voltage level of 1 Rev Page AD5724/AD5734/AD5754 = 2 5 kΩ; CC LOAD Unit Test Conditions/Comments μ step to ±0.03% FSR μ ...
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... AD5724/AD5734/AD5754 TIMING DIAGRAMS SCLK SYNC t 7 SDIN DB23 t 9 LDAC V x OUT V x OUT CLR V x OUT SCLK SYNC t 7 D32B SDIN SDO LDAC DB0 Figure 2. Serial Interface Timing Diagram ...
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... SCLK 1 SYNC DB23 SDIN INPUT WORD SPECIFIES REGISTER TO BE READ DB23 SDO UNDEFINED DB0 DB23 NOP CONDITION DB0 DB23 SELECTED REGISTER DATA CLOCKED OUT Figure 4. Readback Timing Diagram Rev Page AD5724/AD5734/AD5754 24 DB0 DB0 ...
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... AD5724/AD5734/AD5754 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Transient currents 100 mA do not cause SCR latch-up. Table 4. Parameter Rating AV to GND −0 + GND +0 − GND −0 Digital Inputs to GND −0 ...
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... NOTES CONNECT RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. Figure 5. Pin Configuration , input coding is offset binary. When hardwired to GND, input coding is twos CC Rev Page AD5724/AD5734/AD5754 or GND. CC pin, or alternatively, it can be left electrically SS ...
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... Figure 8. AD5724 Integral Nonlinearity Error vs. Code 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 50,000 60,000 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 Figure 10. AD5734 Differential Nonlinearity Error vs. Code 0.04 0.03 0.02 0.01 –0.01 –0.02 –0.03 –0.04 –0.05 3000 3500 4000 Figure 11. AD5724 Differential Nonlinearity Error vs. Code Rev Page /AV = +12V/0V, RANGE = +10V DD ...
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... Figure 16. AD5754 Differential Nonlinearity Error vs. Supply Voltage 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 15.5 16.0 16.5 5.5 Figure 17. AD5754 Differential Nonlinearity Error vs. Supply Voltage Rev Page AD5724/AD5734/AD5754 BIPOLAR 5V MIN UNIPOLAR 5V MIN BIPOLAR 5V MAX UNIPOLAR 5V MAX 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 SUPPLY VOLTAGE (V) BIPOLAR 10V MIN UNIPOLAR 10V MIN BIPOLAR 10V MAX UNIPOLAR 10V MAX 12.0 12.5 13 ...
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... AD5724/AD5734/AD5754 0.02 0.01 0 –0.01 –0.02 –0.03 –0.04 11.5 12.0 12.5 13.0 13.5 14.0 14.5 SUPPLY VOLTAGE (V) Figure 18. AD5754 Total Unadjusted Error vs. Supply Voltage 0.04 0.03 0.02 0.01 0 –0.01 –0.02 –0.03 –0.04 –0.05 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 SUPPLY VOLTAGE (V) Figure 19. AD5754 Total Unadjusted Error vs. Supply Voltage (mA –2 I (mA) SS –4 –6 –8 4.5 6.5 8.5 10.5 AV /AV ( Figure 20. Supply Current vs. Supply Voltage (Dual Supply) ...
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... Figure 28. Full-Scale Settling Time, ±5 V Range –3 Figure 29. Full-Scale Settling Time, +10 V Range Rev Page AD5724/AD5734/AD5754 – TIME (µs) – TIME (µs) – ...
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... AD5724/AD5734/AD5754 –3 – TIME (µs) Figure 30. Full-Scale Settling Time Range 0.020 ±10V RANGE, 0x7FFF TO 0x8000 ±10V RANGE, 0x8000 TO 0x7FFF ±5V RANGE, 0x7FFF TO 0x8000 0.015 ±5V RANGE, 0x8000 TO 0x7FFF +10V RANGE, 0x7FFF TO 0x8000 +10V RANGE, 0x8000 TO 0x7FFF ...
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... /AV = +6.5V/0V, RANGE = + –2 –4 –6 –8 –10 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 CODE Figure 36. AD5734 Total Unadjusted Error vs. Code AD5724/AD5734/AD5754 1.0 AV /AV = +12V/0V, RANGE = +10V /AV = ±12V, RANGE = ±10V /AV = ±6.5V, RANGE = ± 0 ...
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... A typical DNL vs. code plot can be seen in Figure 9. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5724/ AD5734/AD5754 are monotonic over their full operating temperature range. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ...
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... DAC, but is measured when the DAC output is not updated specified in nV-sec and measured with a full-scale code change on the data bus. AD5724/AD5734/AD5754 DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and a subsequent output change of another DAC ...
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... V to ±16 addition, the parts have software-selectable output ranges +10 V, +10.8 V, ±5 V, ±10 V, and ±10.8 V. Data is written to the AD5724/AD5734/ AD5754 in a 24-bit word format via a 3-wire serial interface. The devices also offer an SDO pin to facilitate daisy-chaining or readback ...
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... Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of AD5724/AD5734/AD5754 devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register ...
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... TRANSFER FUNCTION Table 7 to Table 15 show the relationships of the ideal input code to output voltage for the AD5754, AD5734, and AD5724, respec- tively, for all output voltage ranges. For unipolar output ranges, SDO the data coding is straight binary. For bipolar output ranges, the data coding is user-selectable via the BIN/ 2sCOMP pin and can be either offset binary or twos complement ...
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... REFIN × (1/65,536) 0000 0000 0000 0000 0 V AD5724/AD5734/AD5754 Analog Output ±10 V Output Range +4 × REFIN × (32,767/32,768) +4 × REFIN × (32,766/32,768) … +4 × REFIN × (1/32,768 −4 × REFIN × (1/32,768) … ...
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... AD5724/AD5734/AD5754 Ideal Output Voltage to Input Code Relationship—AD5734 Table 10. Bipolar Output, Offset Binary Coding Digital Input MSB LSB 11 1111 1111 1111 11 1111 1111 1110 … … … … 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 … … … … ...
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... REFIN × (1/4096) 0000 0000 0000 0 V AD5724/AD5734/AD5754 Analog Output ±10 V Output Range +4 × REFIN × (2047/2048) +4 × REFIN × (2046/2048) … +4 × REFIN × (1/2048 −4 × REFIN × (1/2048) … −4 × REFIN × (2046/2048) − ...
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... The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel where the data transfer is to take place (see Table 17). The data bits are in positions DB15 to DB0 for the AD5754 (see Table 18), DB15 to DB2 for the AD5734 (see Table 19), and DB15 to DB4 for the AD5724 (see Table 20) ...
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... Don’t care TSD enable Output CLR Value Rev Page AD5724/AD5734/AD5754 DB15 to DB3 DB2 DB1 Don’t care R2 R1 DB2 DB1 NOP, data = don’t care Clamp enable CLR select Clear, data = don’t care Load, data = don’t care ...
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... The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power and thermal status of the AD5724/AD5734/AD5754. The power control register options are shown in Table 26 and Table 27. Table 26. Programming the Power Control Register ...
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... G1 G2 Figure 42. Analog Output Control Circuitry POWER-DOWN MODE Each DAC channel of the AD5724/AD5734/AD5754 can be individually powered down. By default, all channels are in power-down mode. The power status is controlled by the power control register (see Table 26 and Table 27 for details). When a channel is in power-down mode, its output pin is clamped to ground through a resistance of approximately 4 kΩ ...
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... The printed circuit board on which the AD5724/AD5734/AD5754 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5724/AD5734/AD5754 are in a system where multiple devices require an AGND-to- DGND connection, the connection should be made at one point only ...
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... For all interfaces, the DAC output update can be initiated automatically when all the data is clocked in can be performed under the control of LDAC . The contents of the registers can be read using the readback function. Table 28. Some Precision References Recommended for Use with the AD5724/AD5734/AD5754 Part No. Initial Accuracy (mV max) ADR431 ± ...
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... TOP VIEW 1.20 MAX 0.15 0.65 SEATING 0.05 BSC PLANE 0.10 COPLANARITY Figure 45. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] ORDERING GUIDE 1 Model Resolution (Bits) AD5724AREZ 12 AD5724AREZ-REEL7 12 AD5734AREZ 14 AD5734AREZ-REEL7 14 AD5754AREZ 16 AD5754AREZ-REEL7 16 AD5754BREZ 16 AD5754BREZ-REEL7 RoHS Compliant Part. 5.02 5.00 4.95 13 4.50 EXPOSED 4.40 PAD (Pins Up) 4.30 6.40 BSC 12 BOTTOM VIEW 1 ...
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... NOTES AD5724/AD5734/AD5754 Rev Page ...
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... AD5724/AD5734/AD5754 NOTES ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06468-0-7/11(D) Rev Page ...