AD5361 Analog Devices, AD5361 Datasheet - Page 4

• Manufacturer Part Number: AD5361
• Description: 16-Channel, 14-Bit, Serial Input, Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5361

• Resolution (bits): 14bit
• Dac Update Rate: 540kSPS
• Dac Settling Time: 20µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5360/AD5361
SPECIFICATIONS
DV
gain (M), offset (C), and DAC offset registers at default value; all specifications T
Table 1.
Parameter
ACCURACY
REFERENCE INPUTS (VREF0, VREF1)
SIGGND INPUT (SIGGND0 to SIGGND1)
OUTPUT CHARACTERISTICS
MONITOR PIN (MON_OUT)
DIGITAL INPUTS
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
Zero-Scale Error
Full-Scale Error
Span Error of Offset DAC
VOUTx
DC Crosstalk
VREF Input Current
VREF Range
DC Input Impedance
Input Range
SIGGND Gain
Output Voltage Range
Nominal Output Voltage Range
Short-Circuit Current
Load Current
Capacitive Load
DC Output Impedance
Output Impedance
Three-State Leakage Current
Continuous Current Limit
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
CC
DAC Output at Positive Full-Scale
DAC Output at Negative Full-Scale
AD5360
AD5361
AD5360
AD5361
= 2.5 V to 5.5 V; V
3
Temperature Coefficient
2
4
2
2
4
DD
4
2
= 9 V to 16.5 V; V
2
4
B Version
16
14
±4
±1
±15
±20
0.1
1
1
±75
5
180
±10
2/5
50
±0.5
0.995/1.005
V
V
−10 to +10
15
±1
0.5
1000
500
1.7
2.0
0.8
±1
±20
10
±1
2200
100
2
SS
SS
DD
= −16.5 V to −4.5 V; V
+ 1.4
− 1.4
1
Bits
Bits
LSB max
LSB max
μA max
V nominal
μA max
Unit
LSB max
mV max
mV max
% FSR
LSB typ
LSB typ
mV max
ppm FSR/°C typ
μV max
V min/max
kΩ min
V max
Min/max
V min
V max
mA max
mA max
pF max
Ω max
Ω typ
Ω typ
nA typ
mA max
V min
V min
V max
μA max
pF max
Rev. A | Page 4 of 28
REF
= 5 V; AGND = DGND = SIGGND = 0 V; R
Test Conditions/Comments
Guaranteed monotonic by design over temperature
Before calibration
Before calibration
Before calibration
After calibration
After calibration
See the
Includes linearity, offset, and gain drift
Typically 20 μV; measured channel at midscale, full-scale
change on any other channel
Per input; typically ±30 nA
±2% for specified operation
Typically 55 kΩ
I
I
VOUTx
JEDEC compliant
DV
DV
DV
RESET, SYNC, SDI, and SCLK pins
CLR, BIN/2SCOMP, and GPIO pins
LOAD
LOAD
MIN
CC
CC
CC
= 1 mA
= 1 mA
= 3.6 V to 5.5 V
= 2.5 V to 3.6 V
= 2.5 V to 5.5 V
to T
3
Offset DACS
to DV
MAX
, unless otherwise noted.
CC
, V
DD
, or V
section for details
SS
L
= open circuit;