AD5371 Analog Devices, AD5371 Datasheet - Page 4

• Manufacturer Part Number: AD5371
• Description: 40-Channel, 14-Bit, Serial Input, Voltage Output DAC
• Manufacturer: Analog Devices

Specifications of AD5371

• Resolution (bits): 14bit
• Dac Update Rate: 540kSPS
• Dac Settling Time: 20µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5371
SPECIFICATIONS
PERFORMANCE SPECIFICATIONS
DV
R
specifications T
Table 2.
Parameter
ACCURACY
REFERENCE INPUTS (VREF0, VREF1, VREF2)
SIGGND INPUTS (SIGGND0 TO SIGGND4)
OUTPUT CHARACTERISTICS
DIGITAL INPUTS
DIGITAL OUTPUTS (SDO, BUSY)
L
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Zero-Scale Error
Full-Scale Error
Gain Error
Zero-Scale Error
Full-Scale Error
Span Error of Offset DAC
VOUTx Temperature Coefficient
DC Crosstalk
VREFx Input Current
VREFx Range
DC Input Impedance
Input Range
SIGGNDx Gain
Output Voltage Range
Nominal Output Voltage Range
Short-Circuit Current
Load Current
Capacitive Load
DC Output Impedance
Input High Voltage
Input Low Voltage
Input Current
CLR High Impedance Leakage Current
Input Capacitance
Output Low Voltage
Output High Voltage (SDO)
SDO High Impedance Leakage Current
High Impedance Output Capacitance
= open circuit; gain (M), offset (C), and DAC offset registers at default values; temperature range for the AD5371 is −40°C to +85°C; all
CC
(VOUT0 to VOUT39)
= 2.5 V to 5.5 V; V
2
MIN
2
2
to T
2
MAX
DD
, unless otherwise noted.
2
= 9 V to 16.5 V; V
2
2
2
Min
−1
−1
−10
−10
−35
−10
2
50
−0.5
0.995
V
−4
−1
1.7
2.0
−1
−20
DV
−5
SS
SS
= −16.5 V to −8 V; VREF = 3 V; AGND = DGND = SIGGNDx = 0 V; C
CC
+ 1.4
− 0.5
Typ
14
1
1
5
10
Rev. B | Page 4 of 28
1
Max
+1
+1
+10
+10
0.1
+35
120
+10
5
+0.5
1.005
V
+8
15
+1
2200
0.5
0.8
+1
+20
10
0.5
+5
DD
− 1.4
LSB
Unit
Bits
LSB
mV
mV
% FSR
LSB
LSB
mV
ppm
FSR/°C
μV
μA
V
kΩ
V
V
V
mA
mA
pF
Ω
V
V
V
μA
μA
pF
V
V
μA
pF
Test Conditions/Comments
Guaranteed monotonic by design
Before calibration
Before calibration
After calibration
After calibration
See the Offset DACs section for details
Includes linearity, offset, and gain drift
Typically 20 μV; measured channel at midscale,
full-scale change on any other channel
Per input; typically ±30 nA
±2% for specified operation
Typically 55 kΩ
I
VOUTx to DV
DV
DV
DV
Excluding CLR pin
Sinking 200 μA
Sourcing 200 μA
LOAD
CC
CC
CC
= 1 mA
= 2.5 V to 3.6 V
= 3.6 V to 5.5 V
= 2.5 V to 5.5 V
CC
, V
DD
, or V
SS
L
1
= open circuit;