AD5726 Analog Devices, AD5726 Datasheet - Page 8

• Manufacturer Part Number: AD5726
• Description: Quad, 12-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DAC
• Manufacturer: Analog Devices

Specifications of AD5726

• Resolution (bits): 12bit
• Dac Update Rate: 111kSPS
• Dac Settling Time: 9µs
• Max Pos Supply (v): +15.75V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5726
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
16-Lead SSOP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 5. 16-Lead SSOP and 16-Lead SOIC Pin Configuration
Pin No.
V
V
V
V
V
V
AV
AV
OUTD 2
OUTC 3
OUTB 6
OUTA 7
REFN 4
REFP 5
DD 1
SS 8
20-Lead SSOP
1
2
3
4
7
8
9
10
11
12
13
14
5, 6, 15, 16, 17
18
19
20
NC = NO CONNECT
(Not to Scale)
AD5726
TOP VIEW
16
15
14
13
12
11
10
9
GND
SCLK
Mnemonic
AV
V
V
V
V
V
V
AV
SDIN
CS
NC
LDAC
CLR
CLRSEL
OUTD
OUTC
REFN
REFP
OUTB
OUTA
CLRSEL
CLR
LDAC
NC
CS
SCLK
SDIN
GND
DD
SS
Description
Positive Analog Supply Pin. Voltage range is from 5 V to 15 V.
Buffered Analog Output Voltage of DAC D.
Buffered Analog Output Voltage of DAC C.
Negative DAC Reference Input. The voltage applied to this pin defines the zero-scale
output. Allowable range is AV
Positive DAC Reference Input. The voltage applied to this pin defines the full-scale
output voltage. Allowable range is AV
Buffered Analog Output Voltage of DAC B.
Buffered Analog Output Voltage of DAC A.
Negative Analog Supply Pin. Voltage range is from 0 V to −15 V.
Ground Reference Pin.
Serial Data Input. Data must be valid on the rising edge of SCLK. This input is ignored
when CS is high.
Serial Clock Input. Data is clocked into the input register on the rising edge of SCLK.
Active Low Chip Select Pin. This pin must be active for data to be clocked in. This pin
is logically OR’ed with the SCLK input and disables the serial data input when high.
No Internal Connection.
Active Low, Asynchronous Load DAC Input. The data currently contained in the
serial input register is transferred out to the DAC data registers on the falling edge
of LDAC, independent of CS. Input data must remain stable while LDAC is low.
Active Low Input. Sets input register and DAC registers to zero-scale (0x000) or
midscale (0x800), depending on the state of CLRSEL. The data in the serial input
register is unaffected by this control.
Determines the action of CLR. If high, a clear command sets the internal DAC
registers to midscale (0x800). If low, the registers are set to zero (0x000).
Rev. B | Page 8 of 20
SS
to V
Figure 6. 20-Lead SSOP Pin Configuration
V
V
V
V
V
V
REFP
AV
AV
OUTD
OUTC
OUTB
OUTA
REFN
REFP
NC
NC
DD
DD
SS 10
− 2.5 V.
− 2.5 V to V
1
2
3
4
5
6
7
8
9
NC = NO CONNECT
(Not to Scale)
AD5726
TOP VIEW
REFN
+ 2.5 V.
20
19
18
17
16
15
14
13
12
11
CLRSEL
CLR
LDAC
NC
NC
NC
CS
SCLK
SDIN
GND