AD5624 Analog Devices, AD5624 Datasheet - Page 7

• Manufacturer Part Number: AD5624
• Manufacturer: Analog Devices

Specifications of AD5624

• Resolution (bits): 12bit
• Dac Update Rate: 287kSPS
• Dac Settling Time: 3µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
V
V
GND
V
V
SYNC
SCLK
DIN
V
V
OUT
OUT
OUT
OUT
DD
REF
A
B
C
D
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges
of the next 24 clocks. If SYNC is taken high before the 24
and the write sequence is ignored by the device.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 50 MHz.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of
the serial clock input.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. The supply should be decoupled with a 10 μF
capacitor in parallel with a 0.1 μF capacitor to GND.
Reference Voltage Input.
V
V
V
V
OUT
OUT
OUT
OUT
GND
A
B
C
D
Figure 3. Pin Configuration
1
2
3
4
5
Rev. 0 | Page 7 of 24
(Not to Scale)
AD5624/
AD5664
TOP VIEW
10
9
8
7
6
V
V
DIN
SCLK
SYNC
REF
DD
th
falling edge, the rising edge of SYNC acts as an interrupt
AD5624/AD5664