AD9704 Analog Devices, AD9704 Datasheet - Page 38

• Manufacturer Part Number: AD9704
• Manufacturer: Analog Devices

Specifications of AD9704

• Resolution (bits): 8bit
• Dac Update Rate: 175MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.6V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

AD9704/AD9705/AD9706/AD9707
Sleep Operation (Pin Mode)
The
turns off the output current and reduces the total power consumed
by the device. This mode is activated by applying a Logic 1 to
the SLEEP/CSB pin. The SLEEP/CSB pin logic threshold is
equal to 0.5 × DVDD. This digital input also contains an active
pull-down circuit.
The
power down and approximately 5 μs to power back up, when
3.3 V AVDD is used.
Sleep and Power-Down Operation (SPI Mode)
The
functions that can be controlled through the SPI. These power-
down modes can be used to minimize the power dissipation of
the device. The power-down functions are controlled through
Register 0x00, Bit 1 to Bit 3, of the SPI registers. Table 25
summarizes the power-down functions that can be controlled
through the SPI. The power-down mode can be enabled by
writing a Logic 1 to the corresponding bit in Register 0x00.
Table 25. Power-Down Mode Selection
Power-Down
Mode
Clock Off
Sleep
Power Down
SELF-CALIBRATION
The
feature that improves the DNL of the device. Performing a self-
calibration on the device improves device performance in low
frequency applications. The device performance in applications
where the analog output frequencies are above 1 MHz are generally
influenced more by dynamic device behavior than by DNL, and
in these cases, self-calibration is unlikely to provide any benefits
for single-tones, as shown in Figure 86. Figure 87 shows that
self-calibration is helpful up to 20 MHz for two-tone IMD spaced
10 kHz apart.
Figure 85. I
AD9704/AD9705/AD9706/AD9707
AD9704/AD9705/AD9706/AD9707
AD9704/AD9705/AD9706/AD9707
AD9704/AD9705/AD9706/AD9707
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
CLKVDD
10
vs. f
(Reg. 0x00)
Bit Number
1
2
3
20
CLOCK
30
(Differential Clock Mode) at CLKVDD = 1.8 V
f
CLOCK
40
(MSPS)
Functional Description
Turn off clock
Turn off output current
Turn off output current and
internal band gap reference
50
60
have a sleep mode that
take less than 50 ns to
offer three power-down
have a self-calibration
70
80
90
Rev. B | Page 38 of 44
The calibration clock frequency is equal to the DAC clock divided
by the division factor chosen by the DIVSEL value. The frequency
of the calibration clock must be set to under 10 MHz for reliable
calibrations. Best results are obtained by setting DIVSEL[2:0]
(Register 0x0E, Bit 2 to Bit 0) to produce the lowest frequency
calibration clock frequency that the system requirements of the
user allows.
To perform a device self-calibration, use the following procedure:
1
2
3
4
5
6
Figure 86. AD9707 SFDR vs. f
Figure 87. IMD vs. Lower f
88
86
84
82
80
78
88
87
86
85
84
83
82
81
80
79
78
Enable the calibration clock by setting the CALCLK
bit (Register 0x02, Bit 0).
Enable self-calibration by writing 0x40 to Register
0x0F.
Wait approximately 4500 calibration clock cycles. Each
calibration clock cycle is between 2 DAC clock cycles
and 256 DAC clock cycles, depending on the value of
DIVSEL[2:0].
Check if the self-calibration has completed by reading
the CALSTAT bit (Register 0x0F, Bit 7). A Logic 1
indicates the calibration has completed.
When the self-calibration has completed, write 0x00
to Register 0x0F.
Disable the calibration clock by clearing the CALCLK
bit (Register 0x02, Bit 0).
0
0
UNCALIBRATED
UNCALIBRATED
0.2
5
CALIBRATED
CALIBRATED
LOWER
OUT
OUT
f
OUT
at 175 MSPS and I
at 175 MSPS and I
0.4
10
f
(MHz)
OUT
(MHz)
0.6
15
Data Sheet
OUTFS
OUTFS
= 2 mA
= 2 mA
0.8
20