AD9706 Analog Devices, AD9706 Datasheet - Page 30

• Manufacturer Part Number: AD9706
• Manufacturer: Analog Devices

Specifications of AD9706

• Resolution (bits): 12bit
• Dac Update Rate: 175MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.6V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

AD9704/AD9705/AD9706/AD9707
THEORY OF OPERATION
Figure 71 shows a simplified block diagram of the AD9707. The
AD9704/AD9705/AD9706/AD9707
control logic, and full-scale output current control. The DAC
contains a PMOS current source array capable of providing a
nominal full-scale current (I
5 mA. The array is divided into 31 equal currents that make up the
five most significant bits (MSBs). The next four bits, or middle
bits, consist of 15 equal current sources whose value is 1/16 of an
MSB current source. The remaining LSBs are binary weighted frac-
tions of the current sources of the middle bits. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances the
performance for multitone or low amplitude signals and helps
maintain the high output impedance of the DAC (that is,
>200 MΩ).
All of these current sources are switched to one of the two
output nodes (IOUTA or IOUTB) via PMOS differential current
switches. The switches are based on the architecture pioneered
in the
distortion contributed by the switching transient. This switch
architecture also reduces various timing errors and provides
matching complementary drive signals to the inputs of the
differential current switches.
The analog and digital sections of the AD9704/AD9705/AD9706/
AD9707
that can operate independently over a 1.7 V to 3.6 V range. The
digital section, capable of operating at a rate of up to 175 MSPS,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.0 V band gap
voltage reference, and a reference control amplifier.
The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 1 mA to 5 mA via an external
resistor, R
AD9764
have separate power supply inputs (AVDD and DVDD)
SET
, connected to the full-scale adjust (FS ADJ) pin.
family, with further refinements made to reduce
AD9704/AD9705/AD9706/AD9707
OUTFS
) of 2 mA and a maximum of
R
SET
consist of a DAC, digital
1.7V TO
0.1µF
1.7V
3.6V
CLK+
CLK–
TO
3.6V
REFIO
FS ADJ
CLKVDD
CLKCOM
DVDD
DCOM
1.0V REF
DIGITAL INPUTS (DB13 TO DB0) SLEEP/CSB
Figure 71. Simplified Block Diagram
SEGMENTED
dynamic
SWITCHES
Rev. B | Page 30 of 44
LATCHES
AVDD
1.7V TO 3.6V
CURRENT
SOURCE
ARRAY
SWITCHES
LSB
The external resistor, in combination with both the reference
control amplifier and voltage reference, V
current, I
with the proper scaling factor. The full-scale current, I
32 × I
The
setting the output common mode to a value other than ACOM
via the output common mode (OTCM) pin. This facilitates
interfacing the output of the
directly to components that require common-mode levels greater
than 0 V.
SERIAL PERIPHERAL INTERFACE
The
synchronous serial communications port allowing easy interfacing
to many industry-standard microcontrollers and microprocessors.
The serial I/O is compatible with most synchronous transfer
formats, including the Motorola SPI and Intel® SSR protocols.
The interface allows read/write access to all registers that configure
the AD9704/AD9705/AD9706/AD9707. Single or multiple byte
transfers are supported, as well as MSB first or LSB first transfer
formats. The serial interface port of the AD9704/AD9705/AD9706/
AD9707
are referenced to ACOM.
General Operation of the Serial Interface
There are two phases to a communication cycle with the AD9704/
AD9705/AD9706/AD9707. Phase 1 is the instruction cycle, which
is the writing of an instruction byte into the AD9704/AD9705/
AD9706/AD9707, coincident with the first eight SCLK rising
edges. The instruction byte provides the AD9704/AD9705/
AD9706/AD9707
the data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the upcoming
data transfer is read or write, the number of bytes in the data
transfer, and the starting register address for the first byte of the
data transfer.
ACOM
AD9707
AD9704/AD9705/AD9706/AD9707
AD9704/AD9705/AD9706/AD9707
REF
.
is configured as a single pin I/O. SPI terminal voltages
SPI
OTCM
IOUTA
IOUTB
REF
, which is replicated to the segmented current sources
PIN/SPI/RESET
MODE/SDIO
CMODE/SCLK
serial port controller with information regarding
AD9704/AD9705/AD9706/AD9707
serial port is a flexible,
provide the option of
REFIO
, sets the reference
Data Sheet
OUTFS
, is